OUTREGP
OUTREGP( ai->regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );
OUTREGP( regs, RADEON_CRTC_GEN_CNTL,
OUTREGP( regs, RADEON_CRTC_GEN_CNTL, values->crtc_gen_cntl,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc_gen_cntl,
OUTREGP( regs, RADEON_FP_GEN_CNTL, RADEON_FP_FPON | RADEON_FP_TMDS_EN,
OUTREGP( regs, RADEON_FP_GEN_CNTL, 0, ~RADEON_FP_FPON | RADEON_FP_TMDS_EN );
OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_FPON, ~RADEON_FP2_FPON);
OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN);
OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN );
OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_FPON);
OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN);
OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );
OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),
OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, mask );
OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
OUTREGP( regs, RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B );
OUTREGP( regs, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, mask );
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), mask );
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), mask);
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_DISP_REQ_EN_B );
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_REQ_EN_B,
OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON );
OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON );
OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) );
OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 );
OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1);
OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1);
OUTREGP(regs, RADEON_GPIOPAD_A, 1, ~1);
OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1);
OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1);
OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1);
OUTREGP(regs, RADEON_GPIOPAD_A, 0, ~1);
OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1);
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl,
OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 );
OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, ~(
OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
OUTREGP( regs, RADEON_CRTC_GEN_CNTL, crtc_gen_cntl,
OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl,
OUTREGP( regs, RADEON_CRTC_EXT_CNTL, values->crtc_ext_cntl,
OUTREGP( regs, RADEON_CLOCK_CNTL_INDEX,
OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS );
OUTREGP( di->regs, RADEON_GEN_INT_CNTL, RADEON_VIDDMA_MASK, ~RADEON_VIDDMA_MASK );
OUTREGP( regs, RADEON_BUS_CNTL, RADEON_BUS_MASTER_DIS, ~RADEON_BUS_MASTER_DIS );
OUTREGP( regs, RADEON_AIC_CNTL, 0, ~RADEON_PCIGART_TRANSLATE_EN );
OUTREGP( regs, RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
OUTREGP( regs, RADEON_AIC_CNTL, RADEON_PCIGART_TRANSLATE_EN,
OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0,
OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,