headers/private/graphics/radeon/mmio.h

27

OUTREG( (regs), (addr), tmp ); \

src/add-ons/accelerants/3dfx/accelerant.h

188

(OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))

src/add-ons/accelerants/ati/accelerant.h

247

(OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))

src/add-ons/accelerants/ati/mach64.h

505

OUTREG(LCD_DATA, value);

src/add-ons/accelerants/ati/mach64_cursor.cpp

46

OUTREG(CUR_OFFSET, (si.cursorOffset >> 3) + (yOffset << 1));

src/add-ons/accelerants/ati/mach64_cursor.cpp

47

OUTREG(CUR_HORZ_VERT_OFF, (yOffset << 16) | xOffset);

src/add-ons/accelerants/ati/mach64_cursor.cpp

48

OUTREG(CUR_HORZ_VERT_POSN, (y << 16) | x);

src/add-ons/accelerants/ati/mach64_cursor.cpp

98

OUTREG(CUR_CLR0, ~0);

src/add-ons/accelerants/ati/mach64_cursor.cpp

99

OUTREG(CUR_CLR1, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

100

OUTREG(SC_LEFT_RIGHT, ((mode.timing.h_display << 16) | 0 ));

src/add-ons/accelerants/ati/mach64_draw.cpp

101

OUTREG(SC_TOP_BOTTOM, ((mode.timing.v_display << 16) | 0 ));

src/add-ons/accelerants/ati/mach64_draw.cpp

104

OUTREG(DP_BKGD_CLR, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

105

OUTREG(DP_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/ati/mach64_draw.cpp

106

OUTREG(DP_WRITE_MASK, 0xffffffff);

src/add-ons/accelerants/ati/mach64_draw.cpp

107

OUTREG(DP_MIX, (MIX_SRC << 16) | MIX_DST);

src/add-ons/accelerants/ati/mach64_draw.cpp

108

OUTREG(DP_SRC, FRGD_SRC_FRGD_CLR);

src/add-ons/accelerants/ati/mach64_draw.cpp

110

OUTREG(CLR_CMP_CLR, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

111

OUTREG(CLR_CMP_MASK, 0xffffffff);

src/add-ons/accelerants/ati/mach64_draw.cpp

112

OUTREG(CLR_CMP_CNTL, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

124

OUTREG(DP_SRC, BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE);

src/add-ons/accelerants/ati/mach64_draw.cpp

125

OUTREG(DP_FRGD_CLR, color);

src/add-ons/accelerants/ati/mach64_draw.cpp

126

OUTREG(DP_MIX, (MIX_SRC << 16) | MIX_DST);

src/add-ons/accelerants/ati/mach64_draw.cpp

127

OUTREG(DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM | DST_LAST_PEL);

src/add-ons/accelerants/ati/mach64_draw.cpp

136

OUTREG(DST_Y_X, (x << 16) | y);

src/add-ons/accelerants/ati/mach64_draw.cpp

137

OUTREG(DST_HEIGHT_WIDTH, (w << 16) | h);

src/add-ons/accelerants/ati/mach64_draw.cpp

150

OUTREG(DP_SRC, BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE);

src/add-ons/accelerants/ati/mach64_draw.cpp

151

OUTREG(DP_FRGD_CLR, color);

src/add-ons/accelerants/ati/mach64_draw.cpp

152

OUTREG(DP_MIX, (MIX_SRC << 16) | MIX_DST);

src/add-ons/accelerants/ati/mach64_draw.cpp

153

OUTREG(DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM | DST_LAST_PEL);

src/add-ons/accelerants/ati/mach64_draw.cpp

164

OUTREG(DST_Y_X, (x << 16) | y);

src/add-ons/accelerants/ati/mach64_draw.cpp

165

OUTREG(DST_HEIGHT_WIDTH, (w << 16) | 1);

src/add-ons/accelerants/ati/mach64_draw.cpp

176

OUTREG(DP_SRC, BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE);

src/add-ons/accelerants/ati/mach64_draw.cpp

177

OUTREG(DP_MIX, MIX_NOT_DST << 16);

src/add-ons/accelerants/ati/mach64_draw.cpp

178

OUTREG(DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM | DST_LAST_PEL);

src/add-ons/accelerants/ati/mach64_draw.cpp

187

OUTREG(DST_Y_X, (x << 16) | y);

src/add-ons/accelerants/ati/mach64_draw.cpp

188

OUTREG(DST_HEIGHT_WIDTH, (w << 16) | h);

src/add-ons/accelerants/ati/mach64_draw.cpp

201

OUTREG(DP_SRC, FRGD_SRC_BLIT);

src/add-ons/accelerants/ati/mach64_draw.cpp

202

OUTREG(DP_MIX, MIX_SRC << 16);

src/add-ons/accelerants/ati/mach64_draw.cpp

228

OUTREG(DST_CNTL, cmd);

src/add-ons/accelerants/ati/mach64_draw.cpp

229

OUTREG(SRC_Y_X, (src_x << 16) | src_y);

src/add-ons/accelerants/ati/mach64_draw.cpp

230

OUTREG(SRC_HEIGHT1_WIDTH1, ((width + 1) << 16) | (height + 1));

src/add-ons/accelerants/ati/mach64_draw.cpp

231

OUTREG(DST_Y_X, (dest_x << 16) | dest_y);

src/add-ons/accelerants/ati/mach64_draw.cpp

232

OUTREG(DST_HEIGHT_WIDTH, ((width + 1) << 16) | (height + 1));

src/add-ons/accelerants/ati/mach64_draw.cpp

26

OUTREG(GEN_TEST_CNTL, genTestCntl);

src/add-ons/accelerants/ati/mach64_draw.cpp

27

OUTREG(GEN_TEST_CNTL, genTestCntl | GUI_ENGINE_ENABLE);

src/add-ons/accelerants/ati/mach64_draw.cpp

31

OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK);

src/add-ons/accelerants/ati/mach64_draw.cpp

44

OUTREG(MEM_VGA_WP_SEL, 0x00010000);

src/add-ons/accelerants/ati/mach64_draw.cpp

45

OUTREG(MEM_VGA_RP_SEL, 0x00010000);

src/add-ons/accelerants/ati/mach64_draw.cpp

72

OUTREG(DP_PIX_WIDTH, dpPixWidth);

src/add-ons/accelerants/ati/mach64_draw.cpp

73

OUTREG(DP_CHAIN_MASK, dpChainMask);

src/add-ons/accelerants/ati/mach64_draw.cpp

75

OUTREG(CONTEXT_MASK, 0xffffffff);

src/add-ons/accelerants/ati/mach64_draw.cpp

78

OUTREG(DST_OFF_PITCH, (mode.timing.h_display / 8) << 22);

src/add-ons/accelerants/ati/mach64_draw.cpp

79

OUTREG(DST_Y_X, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

80

OUTREG(DST_HEIGHT, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

81

OUTREG(DST_BRES_ERR, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

82

OUTREG(DST_BRES_INC, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

83

OUTREG(DST_BRES_DEC, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

84

OUTREG(DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM | DST_LAST_PEL);

src/add-ons/accelerants/ati/mach64_draw.cpp

87

OUTREG(SRC_OFF_PITCH, (mode.timing.h_display / 8) << 22);

src/add-ons/accelerants/ati/mach64_draw.cpp

88

OUTREG(SRC_Y_X, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

89

OUTREG(SRC_HEIGHT1_WIDTH1, 0x10001);

src/add-ons/accelerants/ati/mach64_draw.cpp

90

OUTREG(SRC_Y_X_START, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

91

OUTREG(SRC_HEIGHT2_WIDTH2, 0x10001);

src/add-ons/accelerants/ati/mach64_draw.cpp

92

OUTREG(SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);

src/add-ons/accelerants/ati/mach64_draw.cpp

96

OUTREG(PAT_REG0, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

97

OUTREG(PAT_REG1, 0);

src/add-ons/accelerants/ati/mach64_draw.cpp

98

OUTREG(PAT_CNTL, 0);

src/add-ons/accelerants/ati/mach64_mode.cpp

110

OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN);

src/add-ons/accelerants/ati/mach64_mode.cpp

140

OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl); // Restore register

src/add-ons/accelerants/ati/mach64_mode.cpp

219

OUTREG(DSP_ON_OFF, dsp_on_off);

src/add-ons/accelerants/ati/mach64_mode.cpp

220

OUTREG(DSP_CONFIG, dsp_config);

src/add-ons/accelerants/ati/mach64_mode.cpp

297

OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN));

src/add-ons/accelerants/ati/mach64_mode.cpp

299

OUTREG(CRTC_H_TOTAL_DISP, crtc_h_total_disp);

src/add-ons/accelerants/ati/mach64_mode.cpp

300

OUTREG(CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);

src/add-ons/accelerants/ati/mach64_mode.cpp

301

OUTREG(CRTC_V_TOTAL_DISP, crtc_v_total_disp);

src/add-ons/accelerants/ati/mach64_mode.cpp

302

OUTREG(CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);

src/add-ons/accelerants/ati/mach64_mode.cpp

304

OUTREG(CRTC_OFF_PITCH, crtc_off_pitch);

src/add-ons/accelerants/ati/mach64_mode.cpp

307

OUTREG(OVR_CLR, 0);

src/add-ons/accelerants/ati/mach64_mode.cpp

308

OUTREG(OVR_WID_LEFT_RIGHT, 0);

src/add-ons/accelerants/ati/mach64_mode.cpp

309

OUTREG(OVR_WID_TOP_BOTTOM, 0);

src/add-ons/accelerants/ati/mach64_mode.cpp

312

OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl);

src/add-ons/accelerants/ati/mach64_overlay.cpp

113

OUTREG(OVERLAY_GRAPHICS_KEY_MSK, keyMask);

src/add-ons/accelerants/ati/mach64_overlay.cpp

114

OUTREG(OVERLAY_GRAPHICS_KEY_CLR, keyColor);

src/add-ons/accelerants/ati/mach64_overlay.cpp

115

OUTREG(OVERLAY_KEY_CNTL, OVERLAY_MIX_FALSE | OVERLAY_MIX_EQUAL);

src/add-ons/accelerants/ati/mach64_overlay.cpp

118

OUTREG(OVERLAY_Y_X_START, OVERLAY_LOCK_START | (x1 << 16) | y1);

src/add-ons/accelerants/ati/mach64_overlay.cpp

119

OUTREG(OVERLAY_Y_X_END, (x2 << 16) | y2);

src/add-ons/accelerants/ati/mach64_overlay.cpp

120

OUTREG(OVERLAY_SCALE_INC, (horzScale << 16) | vertScale);

src/add-ons/accelerants/ati/mach64_overlay.cpp

121

OUTREG(SCALER_HEIGHT_WIDTH, (buffer->width << 16) | buffer->height);

src/add-ons/accelerants/ati/mach64_overlay.cpp

122

OUTREG(VIDEO_FORMAT, videoFormat);

src/add-ons/accelerants/ati/mach64_overlay.cpp

128

OUTREG(BUF0_OFFSET, offset);

src/add-ons/accelerants/ati/mach64_overlay.cpp

129

OUTREG(BUF0_PITCH, buffer->width);

src/add-ons/accelerants/ati/mach64_overlay.cpp

131

OUTREG(SCALER_BUF0_OFFSET, offset);

src/add-ons/accelerants/ati/mach64_overlay.cpp

132

OUTREG(SCALER_BUF0_PITCH, buffer->width);

src/add-ons/accelerants/ati/mach64_overlay.cpp

135

OUTREG(OVERLAY_SCALE_CNTL, SCALE_PIX_EXPAND | OVERLAY_EN | SCALE_EN);

src/add-ons/accelerants/ati/mach64_overlay.cpp

144

OUTREG(OVERLAY_SCALE_CNTL, SCALE_EN); // reset the video

src/add-ons/accelerants/ati/mach64_overlay.cpp

68

OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_EXT_REG_EN); // enable reg block 1

src/add-ons/accelerants/ati/mach64_overlay.cpp

69

OUTREG(OVERLAY_SCALE_CNTL, SCALE_EN); // reset the video

src/add-ons/accelerants/ati/mach64_overlay.cpp

76

OUTREG(SCALER_COLOUR_CNTL, brightness | saturation << 8

src/add-ons/accelerants/ati/mach64_overlay.cpp

78

OUTREG(SCALER_H_COEFF0, 0x0002000);

src/add-ons/accelerants/ati/mach64_overlay.cpp

79

OUTREG(SCALER_H_COEFF1, 0xd06200d);

src/add-ons/accelerants/ati/mach64_overlay.cpp

80

OUTREG(SCALER_H_COEFF2, 0xd0a1c0d);

src/add-ons/accelerants/ati/mach64_overlay.cpp

81

OUTREG(SCALER_H_COEFF3, 0xc0e1a0c);

src/add-ons/accelerants/ati/mach64_overlay.cpp

82

OUTREG(SCALER_H_COEFF4, 0xc14140c);

src/add-ons/accelerants/ati/rage128.h

291

OUTREG(R128_CLOCK_CNTL_DATA, value);

src/add-ons/accelerants/ati/rage128_cursor.cpp

50

OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xOffset << 16) | yOffset);

src/add-ons/accelerants/ati/rage128_cursor.cpp

51

OUTREG(R128_CUR_HORZ_VERT_POSN, R128_CUR_LOCK | (x << 16) | y);

src/add-ons/accelerants/ati/rage128_cursor.cpp

52

OUTREG(R128_CUR_OFFSET, si.cursorOffset + yOffset * 16);

src/add-ons/accelerants/ati/rage128_cursor.cpp

95

OUTREG(R128_CUR_CLR0, ~0);

src/add-ons/accelerants/ati/rage128_cursor.cpp

96

OUTREG(R128_CUR_CLR1, 0);

src/add-ons/accelerants/ati/rage128_dpms.cpp

102

OUTREG(R128_LVDS_GEN_CNTL, genCtrl);

src/add-ons/accelerants/ati/rage128_dpms.cpp

110

OUTREG(R128_LVDS_GEN_CNTL, genCtrl);

src/add-ons/accelerants/ati/rage128_dpms.cpp

113

OUTREG(R128_LVDS_GEN_CNTL, genCtrl);

src/add-ons/accelerants/ati/rage128_dpms.cpp

125

OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)

src/add-ons/accelerants/ati/rage128_dpms.cpp

132

OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)

src/add-ons/accelerants/ati/rage128_draw.cpp

100

OUTREG(R128_SC_TOP_LEFT, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

101

OUTREG(R128_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX

src/add-ons/accelerants/ati/rage128_draw.cpp

108

OUTREG(R128_DP_GUI_MASTER_CNTL, (si.r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

113

OUTREG(R128_DST_BRES_ERR, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

114

OUTREG(R128_DST_BRES_INC, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

115

OUTREG(R128_DST_BRES_DEC, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

116

OUTREG(R128_DP_BRUSH_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/ati/rage128_draw.cpp

117

OUTREG(R128_DP_BRUSH_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/ati/rage128_draw.cpp

118

OUTREG(R128_DP_SRC_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/ati/rage128_draw.cpp

119

OUTREG(R128_DP_SRC_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/ati/rage128_draw.cpp

120

OUTREG(R128_DP_WRITE_MASK, 0xffffffff);

src/add-ons/accelerants/ati/rage128_draw.cpp

135

OUTREG(R128_DP_GUI_MASTER_CNTL, (gInfo.sharedInfo->r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

140

OUTREG(R128_DP_BRUSH_FRGD_CLR, color);

src/add-ons/accelerants/ati/rage128_draw.cpp

141

OUTREG(R128_DP_CNTL, R128_DST_X_LEFT_TO_RIGHT | R128_DST_Y_TOP_TO_BOTTOM);

src/add-ons/accelerants/ati/rage128_draw.cpp

150

OUTREG(R128_DST_Y_X, (y << 16) | x);

src/add-ons/accelerants/ati/rage128_draw.cpp

151

OUTREG(R128_DST_WIDTH_HEIGHT, (w << 16) | h);

src/add-ons/accelerants/ati/rage128_draw.cpp

164

OUTREG(R128_DP_GUI_MASTER_CNTL, (gInfo.sharedInfo->r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

169

OUTREG(R128_DP_BRUSH_FRGD_CLR, color);

src/add-ons/accelerants/ati/rage128_draw.cpp

180

OUTREG(R128_DST_Y_X, (y << 16) | x);

src/add-ons/accelerants/ati/rage128_draw.cpp

181

OUTREG(R128_DST_WIDTH_HEIGHT, (w << 16) | 1);

src/add-ons/accelerants/ati/rage128_draw.cpp

192

OUTREG(R128_DP_GUI_MASTER_CNTL, (gInfo.sharedInfo->r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

198

OUTREG(R128_DP_CNTL, R128_DST_X_LEFT_TO_RIGHT | R128_DST_Y_TOP_TO_BOTTOM);

src/add-ons/accelerants/ati/rage128_draw.cpp

207

OUTREG(R128_DST_Y_X, (y << 16) | x);

src/add-ons/accelerants/ati/rage128_draw.cpp

208

OUTREG(R128_DST_WIDTH_HEIGHT, (w << 16) | h);

src/add-ons/accelerants/ati/rage128_draw.cpp

221

OUTREG(R128_DP_GUI_MASTER_CNTL, (gInfo.sharedInfo->r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

251

OUTREG(R128_DP_CNTL, cmd);

src/add-ons/accelerants/ati/rage128_draw.cpp

252

OUTREG(R128_SRC_Y_X, (src_y << 16) | src_x);

src/add-ons/accelerants/ati/rage128_draw.cpp

253

OUTREG(R128_DST_Y_X, (dest_y << 16) | dest_x);

src/add-ons/accelerants/ati/rage128_draw.cpp

254

OUTREG(R128_DST_HEIGHT_WIDTH, ((height + 1) << 16) | (width + 1));

src/add-ons/accelerants/ati/rage128_draw.cpp

50

OUTREG(R128_GEN_RESET_CNTL, genResetCntl | R128_SOFT_RESET_GUI);

src/add-ons/accelerants/ati/rage128_draw.cpp

52

OUTREG(R128_GEN_RESET_CNTL, genResetCntl & ~R128_SOFT_RESET_GUI);

src/add-ons/accelerants/ati/rage128_draw.cpp

56

OUTREG(R128_CLOCK_CNTL_INDEX, clockCntlIndex);

src/add-ons/accelerants/ati/rage128_draw.cpp

57

OUTREG(R128_GEN_RESET_CNTL, genResetCntl);

src/add-ons/accelerants/ati/rage128_draw.cpp

70

OUTREG(R128_SCALE_3D_CNTL, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

93

OUTREG(R128_DEFAULT_OFFSET, gInfo.sharedInfo->frameBufferOffset);

src/add-ons/accelerants/ati/rage128_draw.cpp

94

OUTREG(R128_DEFAULT_PITCH, mode.timing.h_display / 8);

src/add-ons/accelerants/ati/rage128_draw.cpp

97

OUTREG(R128_AUX_SC_CNTL, 0);

src/add-ons/accelerants/ati/rage128_draw.cpp

98

OUTREG(R128_DEFAULT_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX

src/add-ons/accelerants/ati/rage128_mode.cpp

273

OUTREG(R128_OVR_CLR, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

274

OUTREG(R128_OVR_WID_LEFT_RIGHT, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

275

OUTREG(R128_OVR_WID_TOP_BOTTOM, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

276

OUTREG(R128_OV0_SCALE_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

277

OUTREG(R128_MPP_TB_CONFIG, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

278

OUTREG(R128_MPP_GP_CONFIG, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

279

OUTREG(R128_SUBPIC_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

280

OUTREG(R128_VIPH_CONTROL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

281

OUTREG(R128_I2C_CNTL_1, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

282

OUTREG(R128_GEN_INT_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

283

OUTREG(R128_CAP0_TRIG_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

284

OUTREG(R128_CAP1_TRIG_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

291

OUTREG(R128_BUS_CNTL, busCntl);

src/add-ons/accelerants/ati/rage128_mode.cpp

297

OUTREG(R128_DDA_CONFIG, params.dda_config);

src/add-ons/accelerants/ati/rage128_mode.cpp

298

OUTREG(R128_DDA_ON_OFF, params.dda_on_off);

src/add-ons/accelerants/ati/rage128_mode.cpp

303

OUTREG(R128_CRTC_GEN_CNTL, params.crtc_gen_cntl);

src/add-ons/accelerants/ati/rage128_mode.cpp

308

OUTREG(R128_CRTC_H_TOTAL_DISP, params.crtc_h_total_disp);

src/add-ons/accelerants/ati/rage128_mode.cpp

309

OUTREG(R128_CRTC_H_SYNC_STRT_WID, params.crtc_h_sync_strt_wid);

src/add-ons/accelerants/ati/rage128_mode.cpp

310

OUTREG(R128_CRTC_V_TOTAL_DISP, params.crtc_v_total_disp);

src/add-ons/accelerants/ati/rage128_mode.cpp

311

OUTREG(R128_CRTC_V_SYNC_STRT_WID, params.crtc_v_sync_strt_wid);

src/add-ons/accelerants/ati/rage128_mode.cpp

312

OUTREG(R128_CRTC_OFFSET, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

313

OUTREG(R128_CRTC_OFFSET_CNTL, 0);

src/add-ons/accelerants/ati/rage128_mode.cpp

314

OUTREG(R128_CRTC_PITCH, params.crtc_pitch);

src/add-ons/accelerants/ati/rage128_mode.cpp

398

OUTREG(R128_PALETTE_DATA, (i << 16) | (i << 8) | i );

src/add-ons/accelerants/ati/rage128_mode.cpp

420

OUTREG(R128_CRTC_OFFSET, address);

src/add-ons/accelerants/ati/rage128_mode.cpp

441

OUTREG(R128_PALETTE_DATA, ((colorData[0] << 16) // red

src/add-ons/accelerants/ati/rage128_overlay.cpp

136

OUTREG(R128_OV0_REG_LOAD_CNTL, 1);

src/add-ons/accelerants/ati/rage128_overlay.cpp

140

OUTREG(R128_OV0_H_INC, horzInc | ((horzInc >> 1) << 16));

src/add-ons/accelerants/ati/rage128_overlay.cpp

141

OUTREG(R128_OV0_STEP_BY, stepBy | (stepBy << 8));

src/add-ons/accelerants/ati/rage128_overlay.cpp

142

OUTREG(R128_OV0_Y_X_START, x1 | y1 << 16);

src/add-ons/accelerants/ati/rage128_overlay.cpp

143

OUTREG(R128_OV0_Y_X_END, x2 | y2 << 16);

src/add-ons/accelerants/ati/rage128_overlay.cpp

144

OUTREG(R128_OV0_V_INC, vertInc);

src/add-ons/accelerants/ati/rage128_overlay.cpp

145

OUTREG(R128_OV0_P1_BLANK_LINES_AT_TOP,

src/add-ons/accelerants/ati/rage128_overlay.cpp

147

OUTREG(R128_OV0_VID_BUF_PITCH0_VALUE, buffer->bytes_per_row);

src/add-ons/accelerants/ati/rage128_overlay.cpp

151

OUTREG(R128_OV0_P1_X_START_END, (width - 1) | (left << 16));

src/add-ons/accelerants/ati/rage128_overlay.cpp

153

OUTREG(R128_OV0_P2_X_START_END, (width - 1) | (left << 16));

src/add-ons/accelerants/ati/rage128_overlay.cpp

154

OUTREG(R128_OV0_P3_X_START_END, (width - 1) | (left << 16));

src/add-ons/accelerants/ati/rage128_overlay.cpp

155

OUTREG(R128_OV0_VID_BUF0_BASE_ADRS, offset);

src/add-ons/accelerants/ati/rage128_overlay.cpp

156

OUTREG(R128_OV0_P1_V_ACCUM_INIT, p1_v_accum_init);

src/add-ons/accelerants/ati/rage128_overlay.cpp

157

OUTREG(R128_OV0_P23_V_ACCUM_INIT, 0);

src/add-ons/accelerants/ati/rage128_overlay.cpp

158

OUTREG(R128_OV0_P1_H_ACCUM_INIT, p1_h_accum_init);

src/add-ons/accelerants/ati/rage128_overlay.cpp

159

OUTREG(R128_OV0_P23_H_ACCUM_INIT, p23_h_accum_init);

src/add-ons/accelerants/ati/rage128_overlay.cpp

161

OUTREG(R128_OV0_SCALE_CNTL, 0x41FF8B03);

src/add-ons/accelerants/ati/rage128_overlay.cpp

162

OUTREG(R128_OV0_REG_LOAD_CNTL, 0);

src/add-ons/accelerants/ati/rage128_overlay.cpp

171

OUTREG(R128_OV0_SCALE_CNTL, 0); // reset the video

src/add-ons/accelerants/ati/rage128_overlay.cpp

77

OUTREG(R128_OV0_SCALE_CNTL, 0);

src/add-ons/accelerants/ati/rage128_overlay.cpp

78

OUTREG(R128_OV0_EXCLUSIVE_HORZ, 0);

src/add-ons/accelerants/ati/rage128_overlay.cpp

79

OUTREG(R128_OV0_AUTO_FLIP_CNTL, 0);

src/add-ons/accelerants/ati/rage128_overlay.cpp

80

OUTREG(R128_OV0_FILTER_CNTL, 0x0000000f);

src/add-ons/accelerants/ati/rage128_overlay.cpp

84

OUTREG(R128_OV0_COLOUR_CNTL, brightness | saturation << 8

src/add-ons/accelerants/ati/rage128_overlay.cpp

87

OUTREG(R128_OV0_GRAPHICS_KEY_MSK, keyMask);

src/add-ons/accelerants/ati/rage128_overlay.cpp

88

OUTREG(R128_OV0_GRAPHICS_KEY_CLR, keyColor);

src/add-ons/accelerants/ati/rage128_overlay.cpp

89

OUTREG(R128_OV0_KEY_CNTL, R128_GRAPHIC_KEY_FN_NE);

src/add-ons/accelerants/ati/rage128_overlay.cpp

90

OUTREG(R128_OV0_TEST, 0);

src/add-ons/accelerants/intel_810/i810_regs.h

122

(OUTREG(addr, (INREG(addr) & ~mask) | (value & mask)))

src/add-ons/accelerants/radeon/Acceleration.c

100

OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1));

src/add-ons/accelerants/radeon/Acceleration.c

166

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)

src/add-ons/accelerants/radeon/Acceleration.c

171

OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);

src/add-ons/accelerants/radeon/Acceleration.c

172

OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));

src/add-ons/accelerants/radeon/Acceleration.c

178

OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);

src/add-ons/accelerants/radeon/Acceleration.c

179

OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom - list->top + 1));

src/add-ons/accelerants/radeon/Acceleration.c

249

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)

src/add-ons/accelerants/radeon/Acceleration.c

255

OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));

src/add-ons/accelerants/radeon/Acceleration.c

261

OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);

src/add-ons/accelerants/radeon/Acceleration.c

262

OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom - list->top + 1));

src/add-ons/accelerants/radeon/Acceleration.c

330

OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL, 0

src/add-ons/accelerants/radeon/Acceleration.c

338

OUTREG( ai->regs, RADEON_DST_LINE_PATCOUNT, 0x55 << RADEON_BRES_CNTL_SHIFT);

src/add-ons/accelerants/radeon/Acceleration.c

342

OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);

src/add-ons/accelerants/radeon/Acceleration.c

352

OUTREG( ai->regs, RADEON_DST_LINE_START, (y << 16) | x);

src/add-ons/accelerants/radeon/Acceleration.c

353

OUTREG( ai->regs, RADEON_DST_LINE_END, ((y) << 16) | (x + width));

src/add-ons/accelerants/radeon/Acceleration.c

408

OUTREG( ai->regs, RADEON_RB3D_CNTL, 0 );

src/add-ons/accelerants/radeon/Acceleration.c

463

OUTREG( ai->regs, RADEON_DEFAULT_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

464

OUTREG( ai->regs, RADEON_DST_PITCH_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

465

OUTREG( ai->regs, RADEON_SRC_PITCH_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

467

OUTREG( ai->regs, RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX

src/add-ons/accelerants/radeon/Acceleration.c

470

OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL,

src/add-ons/accelerants/radeon/Acceleration.c

483

OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

484

OUTREG( ai->regs, RADEON_DP_BRUSH_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/radeon/Acceleration.c

485

OUTREG( ai->regs, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

486

OUTREG( ai->regs, RADEON_DP_SRC_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/radeon/Acceleration.c

487

OUTREG( ai->regs, RADEON_DP_WRITE_MASK, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

73

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT

src/add-ons/accelerants/radeon/Acceleration.c

92

OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0)

src/add-ons/accelerants/radeon/Acceleration.c

96

OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left);

src/add-ons/accelerants/radeon/Acceleration.c

97

OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left);

src/add-ons/accelerants/radeon/CP.c

347

OUTREG( ai->regs, RADEON_CP_RB_WPTR, cp->ring.tail );

src/add-ons/accelerants/radeon/Cursor.c

197

OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK

src/add-ons/accelerants/radeon/Cursor.c

200

OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK

src/add-ons/accelerants/radeon/Cursor.c

203

OUTREG( ai->regs, RADEON_CUR_OFFSET,

src/add-ons/accelerants/radeon/Cursor.c

206

OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK

src/add-ons/accelerants/radeon/Cursor.c

209

OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK

src/add-ons/accelerants/radeon/Cursor.c

212

OUTREG( ai->regs, RADEON_CUR2_OFFSET,

src/add-ons/accelerants/radeon/Cursor.c

235

OUTREG( ai->regs, RADEON_CRTC_GEN_CNTL, tmp );

src/add-ons/accelerants/radeon/Cursor.c

245

OUTREG( ai->regs, RADEON_CRTC2_GEN_CNTL, tmp );

src/add-ons/accelerants/radeon/Cursor.c

25

OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff );

src/add-ons/accelerants/radeon/Cursor.c

26

OUTREG( ai->regs, RADEON_CUR_CLR1, 0 );

src/add-ons/accelerants/radeon/Cursor.c

28

OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff );

src/add-ons/accelerants/radeon/Cursor.c

29

OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 );

src/add-ons/accelerants/radeon/EngineManagment.c

86

OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);

src/add-ons/accelerants/radeon/EngineManagment.c

87

OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |

src/add-ons/accelerants/radeon/SetDisplayMode.c

100

OUTREG( regs, RADEON_CRTC_MORE_CNTL, 0 );

src/add-ons/accelerants/radeon/SetDisplayMode.c

263

OUTREG( regs, RADEON_SURFACE_CNTL, surface_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

334

OUTREG( ai->regs, RADEON_GEN_INT_CNTL, int_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

339

OUTREG( ai->regs, RADEON_GEN_INT_STATUS, int_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

90

OUTREG( regs, common_regs[i].reg, common_regs[i].val );

src/add-ons/accelerants/radeon/crtc.c

143

OUTREG( ai->regs, crtc->crtc_idx == 0 ? RADEON_CRTC_OFFSET : RADEON_CRTC2_OFFSET, offset );

src/add-ons/accelerants/radeon/crtc.c

30

OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp );

src/add-ons/accelerants/radeon/crtc.c

31

OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

32

OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp );

src/add-ons/accelerants/radeon/crtc.c

33

OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

34

OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl );

src/add-ons/accelerants/radeon/crtc.c

35

OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch );

src/add-ons/accelerants/radeon/crtc.c

44

OUTREG( regs, RADEON_CRTC2_H_TOTAL_DISP, values->crtc_h_total_disp );

src/add-ons/accelerants/radeon/crtc.c

45

OUTREG( regs, RADEON_CRTC2_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

46

OUTREG( regs, RADEON_CRTC2_V_TOTAL_DISP, values->crtc_v_total_disp );

src/add-ons/accelerants/radeon/crtc.c

47

OUTREG( regs, RADEON_CRTC2_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

48

OUTREG( regs, RADEON_CRTC2_OFFSET_CNTL, values->crtc_offset_cntl );

src/add-ons/accelerants/radeon/crtc.c

49

OUTREG( regs, RADEON_CRTC2_PITCH, values->crtc_pitch );

src/add-ons/accelerants/radeon/dpms.c

281

OUTREG( ai->regs, RADEON_TV_LINEAR_GAIN_SETTINGS,

src/add-ons/accelerants/radeon/flat_panel.c

112

OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );

src/add-ons/accelerants/radeon/flat_panel.c

113

OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );

src/add-ons/accelerants/radeon/flat_panel.c

266

OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

267

OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

270

OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

271

OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

277

OUTREG( regs, RADEON_GRPH_BUFFER_CNTL,

src/add-ons/accelerants/radeon/flat_panel.c

282

OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

283

OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

284

OUTREG( regs, RADEON_BIOS_6_SCRATCH, values->bios_6_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

311

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

315

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

319

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl | RADEON_LVDS_BLON );

src/add-ons/accelerants/radeon/flat_panel.c

321

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/internal_tv_out.c

135

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_RD);

src/add-ons/accelerants/radeon/internal_tv_out.c

148

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0);

src/add-ons/accelerants/radeon/internal_tv_out.c

168

OUTREG( regs, RADEON_TV_HOST_WRITE_DATA, value );

src/add-ons/accelerants/radeon/internal_tv_out.c

169

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_WT );

src/add-ons/accelerants/radeon/internal_tv_out.c

182

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0 );

src/add-ons/accelerants/radeon/internal_tv_out.c

210

OUTREG( ai->regs, RADEON_TV_MASTER_CNTL,

src/add-ons/accelerants/radeon/internal_tv_out.c

99

OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) );

src/add-ons/accelerants/radeon/monitor_detection.c

112

OUTREG(regs, RADEON_CRTC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

121

OUTREG(regs, RADEON_DAC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

128

OUTREG(regs, RADEON_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

143

OUTREG(regs, RADEON_DAC_CNTL, old_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

144

OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

145

OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

189

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

196

OUTREG(regs, RADEON_TV_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

202

OUTREG(regs, RADEON_DAC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

209

OUTREG(regs, RADEON_DAC_CNTL2, value);

src/add-ons/accelerants/radeon/monitor_detection.c

218

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

219

OUTREG(regs, RADEON_DAC_EXT_CNTL, 0);

src/add-ons/accelerants/radeon/monitor_detection.c

220

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

221

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

252

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

257

OUTREG(regs, RADEON_TV_DAC_CNTL, RADEON_TV_DAC_CNTL_NBLANK

src/add-ons/accelerants/radeon/monitor_detection.c

262

OUTREG(regs, RADEON_DAC_EXT_CNTL, RADEON_DAC2_FORCE_BLANK_OFF_EN

src/add-ons/accelerants/radeon/monitor_detection.c

269

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2 | RADEON_DAC2_CLK_SEL_CRT

src/add-ons/accelerants/radeon/monitor_detection.c

278

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

279

OUTREG(regs, RADEON_DAC_EXT_CNTL, 0);

src/add-ons/accelerants/radeon/monitor_detection.c

280

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

281

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

347

OUTREG(regs, RADEON_DAC_CNTL2, value);

src/add-ons/accelerants/radeon/monitor_detection.c

364

OUTREG(regs, RADEON_TV_MASTER_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

376

OUTREG(regs, RADEON_TV_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

387

OUTREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

404

OUTREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL, old_pre_dac_mux_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

405

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

406

OUTREG(regs, RADEON_TV_MASTER_CNTL, old_tv_master_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

407

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

408

OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

409

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

434

OUTREG(regs, RADEON_DAC_CNTL2, RADEON_DAC2_CLK_SEL_CRT);

src/add-ons/accelerants/radeon/monitor_detection.c

441

OUTREG(regs, RADEON_CRTC2_GEN_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

447

OUTREG(regs, RADEON_DAC_EXT_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

455

OUTREG(regs, RADEON_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

464

OUTREG(regs, RADEON_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

488

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

489

OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

490

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

491

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

65

OUTREG(regs, info->port, value);

src/add-ons/accelerants/radeon/monitor_routing.c

424

OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

425

OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 );

src/add-ons/accelerants/radeon/monitor_routing.c

428

OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

438

OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug );

src/add-ons/accelerants/radeon/monitor_routing.c

442

OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

462

OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

466

OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl );

src/add-ons/accelerants/radeon/overlay.c

1022

OUTREG( ai->regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset);

src/add-ons/accelerants/radeon/overlay.c

1025

OUTREG( ai->regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

263

OUTREG( regs, RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvRY );

src/add-ons/accelerants/radeon/overlay.c

264

OUTREG( regs, RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr );

src/add-ons/accelerants/radeon/overlay.c

265

OUTREG( regs, RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvGY );

src/add-ons/accelerants/radeon/overlay.c

266

OUTREG( regs, RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr );

src/add-ons/accelerants/radeon/overlay.c

267

OUTREG( regs, RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvBY );

src/add-ons/accelerants/radeon/overlay.c

268

OUTREG( regs, RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr );

src/add-ons/accelerants/radeon/overlay.c

336

OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min32 );

src/add-ons/accelerants/radeon/overlay.c

337

OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max32 );

src/add-ons/accelerants/radeon/overlay.c

338

OUTREG( regs, RADEON_OV0_KEY_CNTL,

src/add-ons/accelerants/radeon/overlay.c

68

OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );

src/add-ons/accelerants/radeon/overlay.c

69

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

70

OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients

src/add-ons/accelerants/radeon/overlay.c

75

OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |

src/add-ons/accelerants/radeon/overlay.c

78

OUTREG( regs, RADEON_OV0_TEST, 0 );

src/add-ons/accelerants/radeon/overlay.c

81

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

83

OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN,

src/add-ons/accelerants/radeon/overlay.c

849

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK );

src/add-ons/accelerants/radeon/overlay.c

856

OUTREG( regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset );

src/add-ons/accelerants/radeon/overlay.c

857

OUTREG( regs, RADEON_OV0_VID_BUF_PITCH0_VALUE, node->buffer.bytes_per_row );

src/add-ons/accelerants/radeon/overlay.c

858

OUTREG( regs, RADEON_OV0_H_INC, p1_h_inc | (p23_h_inc << 16) );

src/add-ons/accelerants/radeon/overlay.c

859

OUTREG( regs, RADEON_OV0_STEP_BY, factors->p1_step_by | (factors->p23_step_by << 8) );

src/add-ons/accelerants/radeon/overlay.c

860

OUTREG( regs, RADEON_OV0_V_INC, v_inc );

src/add-ons/accelerants/radeon/overlay.c

862

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

865

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

869

OUTREG( regs, RADEON_OV0_P1_BLANK_LINES_AT_TOP,

src/add-ons/accelerants/radeon/overlay.c

871

OUTREG( regs, RADEON_OV0_P1_X_START_END, p1_x_end | (p1_x_start << 16) );

src/add-ons/accelerants/radeon/overlay.c

872

OUTREG( regs, RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init );

src/add-ons/accelerants/radeon/overlay.c

873

OUTREG( regs, RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init );

src/add-ons/accelerants/radeon/overlay.c

875

OUTREG( regs, RADEON_OV0_P23_BLANK_LINES_AT_TOP,

src/add-ons/accelerants/radeon/overlay.c

877

OUTREG( regs, RADEON_OV0_P2_X_START_END,

src/add-ons/accelerants/radeon/overlay.c

879

OUTREG( regs, RADEON_OV0_P3_X_START_END,

src/add-ons/accelerants/radeon/overlay.c

881

OUTREG( regs, RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init );

src/add-ons/accelerants/radeon/overlay.c

882

OUTREG( regs, RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init );

src/add-ons/accelerants/radeon/overlay.c

884

OUTREG( regs, RADEON_OV0_TEST, node->test_reg );

src/add-ons/accelerants/radeon/overlay.c

89

OUTREG( regs, std_gamma[i].reg,

src/add-ons/accelerants/radeon/overlay.c

897

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |

src/add-ons/accelerants/radeon/overlay.c

902

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl);

src/add-ons/accelerants/radeon/overlay.c

906

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |

src/add-ons/accelerants/radeon/overlay.c

913

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL,

src/add-ons/accelerants/radeon/overlay.c

916

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

936

OUTREG( ai->regs, RADEON_OV0_SCALE_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

989

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

996

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/palette.c

104

OUTREG( ai->regs, RADEON_DAC_CNTL2,

src/add-ons/accelerants/radeon/palette.c

108

OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );

src/add-ons/accelerants/radeon/palette.c

111

OUTREG( ai->regs, RADEON_PALETTE_DATA,

src/add-ons/accelerants/radeon/palette.c

41

OUTREG( ai->regs, RADEON_DAC_CNTL2,

src/add-ons/accelerants/radeon/palette.c

45

OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );

src/add-ons/accelerants/radeon/palette.c

48

OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

234

OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

243

OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset &

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

253

OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

255

OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

258

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

260

OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

266

OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

312

OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

315

OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

316

OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

351

OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

356

OUTREG( regs, RADEON_CP_RB_CNTL, radeon_log2( cp->ring.size / 2 ));

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

362

OUTREG( regs, RADEON_CP_RB_WPTR_DELAY, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

367

OUTREG( regs, RADEON_CP_RB_RPTR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

368

OUTREG( regs, RADEON_CP_RB_WPTR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

383

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

415

OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

422

OUTREG( regs, RADEON_SCRATCH_ADDR, cp->feedback.scratch_vm_start );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

423

OUTREG( regs, RADEON_SCRATCH_UMSK, 0x3f );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

437

OUTREG( regs, RADEON_SCRATCH_UMSK, 0x0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

521

OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

545

OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

555

OUTREG( di->regs, RADEON_ISYNC_CNTL,

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

588

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

170

OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

41

OUTREG( di->regs, RADEON_GEN_INT_STATUS, RADEON_VIDDMA_AK );

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

294

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

932

OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size * 1024);

src/add-ons/kernel/drivers/graphics/radeon/bios.c

940

OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size);

src/add-ons/kernel/drivers/graphics/radeon/init.c

443

OUTREG( di->regs, RADEON_DAC_CNTL2, di->dac2_cntl );

src/add-ons/kernel/drivers/graphics/radeon/irq.c

119

OUTREG(regs, RADEON_GEN_INT_STATUS, int_status);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

21

OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

93

OUTREG(regs, RADEON_CAP_INT_STATUS, cap_status);

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

163

OUTREG( regs, RADEON_AIC_PT_BASE, di->pci_gart.GATT.phys );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

167

OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

168

OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

172

OUTREG( regs, RADEON_MC_AGP_LOCATION, 0xffffffc0 /* EK magic numbers from X.org

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

177

OUTREG( regs, RADEON_AGP_COMMAND, 0 );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

182

OUTREG( regs, RADEON_MC_FB_LOCATION,

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

188

OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

189

OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

190

OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

52

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

54

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

78

OUTREG( regs, RADEON_CLOCK_CNTL_DATA, val );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

114

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x3000);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

127

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

145

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

166

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

196

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

203

OUTREG( regs, RADEON_VIPH_REG_DATA, data );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

240

OUTREG( regs, RADEON_VIPH_REG_ADDR,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

258

OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

310

OUTREG( regs, RADEON_VIPH_CONTROL, 4 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

312

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

314

OUTREG( regs, RADEON_VIPH_DV_LAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

320

OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

321

OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

323

OUTREG( regs, RADEON_VIPH_CONTROL, 9 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

325

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

327

OUTREG( regs, RADEON_VIPH_DV_LAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

333

OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

334

OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

358

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

36

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

373

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);