AR_PHY_TIMING_CTRL4
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) {
val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);
val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);
if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
(AR_PHY_TIMING_CTRL4 + ((_i) << 12))