MASTER_CLK_SEL_DIS
(val & MASTER_CLK_SEL_DIS) == 0) {
val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
(val & MASTER_CLK_SEL_DIS) != 0) {
val &= ~MASTER_CLK_SEL_DIS;
CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
master &= ~MASTER_CLK_SEL_DIS;
reg |= MASTER_CLK_SEL_DIS;