IWN_SCHED_BASE
#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)