IWM_WRITE
IWM_WRITE(sc,
IWM_WRITE(sc,
IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
IWM_WRITE(sc, wreg, hw & ~7);
IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);
IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask);
IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK);
IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK);
IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC);
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
IWM_WRITE(sc, IWM_CSR_MSIX_AUTOMASK_ST_AD, 1 << vector);
IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff);
IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);
IWM_WRITE(sc, IWM_CSR_INT, ~0);
IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, ~0);
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD,
IWM_WRITE(sc, IWM_CSR_DRAM_INT_TBL_REG,
IWM_WRITE(sc, IWM_CSR_INT, ~0);
IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, ~0);
IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, ~0);
IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
IWM_WRITE(sc,
IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, val);
IWM_WRITE(sc, IWM_RFH_Q0_FRBDCB_WIDX_TRG, 8);
IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RDPTR, 0);
IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
IWM_WRITE(sc,
IWM_WRITE(sc,
IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG,
IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8);
IWM_WRITE(sc, IWM_FH_KW_MEM_ADDR_REG, sc->kw_dma.paddr >> 4);
IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid),
IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0);
IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | idx);
IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl),
IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL),
IWM_WRITE(sc, IWM_CSR_RESET, 0);
IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val);
IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFF);
IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
IWM_WRITE(sc, IWM_CSR_INT, ~0);
IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);
IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR,
IWM_WRITE(sc, IWM_CSR_INT, ~0);
IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);
IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);
IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
IWM_WRITE(sc, IWM_CSR_LED_REG, IWM_CSR_LED_REG_TURN_ON);
IWM_WRITE(sc, IWM_CSR_LED_REG, IWM_CSR_LED_REG_TURN_OFF);
IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))