IWM_SCD_BASE
#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
return IWM_SCD_BASE + 0x18 + chnl * 4;
return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
return IWM_SCD_BASE + 0x68 + chnl * 4;
return IWM_SCD_BASE + 0x2B4 + chnl * 4;
return IWM_SCD_BASE + 0x10c + chnl * 4;
return IWM_SCD_BASE + 0x334 + chnl * 4;