INTEL_PIPE_A
#define FDI_RX_CTL(pipe) (_FDI_RXA_CTL + (_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A))
#define FDI_RX_MISC(pipe) (_FDI_RXA_MISC + (_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A))
#define FDI_RX_IIR(pipe) (_FDI_RXA_IIR + (_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A))
#define FDI_RX_IMR(pipe) (_FDI_RXA_IMR + (_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A))
#define FDI_RX_TUSIZE1(pipe) (_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 - _FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A))
#define FDI_RX_TUSIZE2(pipe) (_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 - _FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A))
#define FDI_TX_CTL(pipe) (_FDI_TXA_CTL + (_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A))
TRACE("%s: FDI Link %s:\n", __func__, (fPipeIndex == INTEL_PIPE_A) ? "A" : "B");
if (fPipeIndex == INTEL_PIPE_A) {
return INTEL_PIPE_A;
return INTEL_PIPE_A;
if (fPipe->Index() == INTEL_PIPE_A)
return INTEL_PIPE_A;
return INTEL_PIPE_A;
return INTEL_PIPE_A;
if (pipe->Index() == INTEL_PIPE_A)
return INTEL_PIPE_A;
return INTEL_PIPE_A;
return INTEL_PIPE_A;
gInfo->pipes[i] = new(std::nothrow) Pipe(INTEL_PIPE_A);
if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_A)) != 0) {
const uint32 regIdentity = PCH_INTERRUPT_PIPE_IDENTITY_BDW(INTEL_PIPE_A);
interrupt &= ~PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_A);
if (pipe == INTEL_PIPE_A) {
const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, true);
if (which.HasPipe(INTEL_PIPE_A))
const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, false);
which.SetPipe(INTEL_PIPE_A);
case INTEL_PIPE_A:
if (which.HasPipe(INTEL_PIPE_A)) {
intel_clear_pipe_interrupt(info, INTEL_PIPE_A);
gen8_enable_interrupts(info, INTEL_PIPE_A, true);
g35_clear_interrupt_status(info, INTEL_PIPE_A);
which.SetPipe(INTEL_PIPE_A);