INREG
uint32 tmp = INREG( (regs), (addr) ); \
(OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))
(OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))
return INREG(LCD_DATA);
uint32 tmp = INREG(CRTC_GEN_CNTL);
uint32 genTestCntl = INREG(GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE;
OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK);
uint32 dspConfig = INREG(DSP_CONFIG);
uint32 memCntl = INREG(MEM_CNTL);
while ((INREG(FIFO_STAT) & 0xffff) > (0x8000ul >> entries)) ;
while (INREG(GUI_STAT) & ENGINE_BUSY) ;
uint32 memCntl = INREG(MEM_CNTL);
int memType = INREG(CONFIG_STAT0) & 0x7;
uint32 crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
uint32 crtc_gen_cntl = INREG(CRTC_GEN_CNTL) &
OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_EXT_REG_EN); // enable reg block 1
return INREG(R128_CLOCK_CNTL_DATA);
genCtrl = INREG(R128_LVDS_GEN_CNTL);
OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
uint32 tmp = INREG(R128_CRTC_EXT_CNTL);
genCtrl = INREG(R128_LVDS_GEN_CNTL);
if ( ! (INREG(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
uint32 clockCntlIndex = INREG(R128_CLOCK_CNTL_INDEX);
uint32 genResetCntl = INREG(R128_GEN_RESET_CNTL);
INREG(R128_GEN_RESET_CNTL);
INREG(R128_GEN_RESET_CNTL);
INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
INREG(R128_GUI_STAT),
INREG(R128_GUI_PROBE));
si.videoMemSize = INREG(R128_CONFIG_MEMSIZE);
switch (INREG(R128_MEM_CNTL) & 0x3) {
if (INREG(R128_FP_PANEL_CNTL) & R128_FP_DIGON) // don't know if this is correct
if (INREG(R128_LVDS_GEN_CNTL) & R128_LVDS_ON)
uint32 slots = INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
INREG(R128_GUI_STAT),
INREG(R128_GUI_PROBE));
if ( ! (INREG(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
uint32 busCntl = INREG(R128_BUS_CNTL);
while (!(INREG(R128_OV0_REG_LOAD_CNTL) & (1 << 3)))
(OUTREG(addr, (INREG(addr) & ~mask) | (value & mask)))
INREG( ai->regs, RADEON_CP_RB_RPTR );
tmp = INREG( ai->regs, RADEON_CRTC_GEN_CNTL );
tmp = INREG( ai->regs, RADEON_CRTC2_GEN_CNTL );
SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 ));
SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL ));
SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL ));
SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL ));
SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( regs, RADEON_FP_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_FP2_GEN_CNTL %08X ", INREG( regs, RADEON_FP2_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_LVDS_GEN_CNTL %08X ", INREG( regs, RADEON_LVDS_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_TMDS_PLL_CNTL %08X ", INREG( regs, RADEON_TMDS_PLL_CNTL ));
SHOW_FLOW( 0, "RADEON_TMDS_TRANSMITTER_CNTL %08X ", INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL ));
SHOW_FLOW( 0, "RADEON_FP_H_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_V_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_H2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_V2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ));
int_cntl = INREG( ai->regs, RADEON_GEN_INT_CNTL );
si->dac_cntl2 = INREG( ai->regs, RADEON_DAC_CNTL2 );
tmp = INREG( di->regs, RADEON_CRTC_EXT_CNTL );
tmp = INREG( di->regs, RADEON_CRTC2_GEN_CNTL );
int slots = INREG( ai->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );
values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );
values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID );
values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID );
values->bios_4_scratch = INREG( regs, RADEON_BIOS_4_SCRATCH );
values->bios_5_scratch = INREG( regs, RADEON_BIOS_5_SCRATCH );
values->bios_6_scratch = INREG( regs, RADEON_BIOS_6_SCRATCH );
values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
INREG( regs, RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
tmp = INREG( regs, RADEON_LVDS_GEN_CNTL);
status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );
res = INREG( regs, RADEON_TV_HOST_READ_DATA );
status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );
INREG( regs, mapping->address );
if (INREG(ai->regs, RADEON_FP_GEN_CNTL) & (1 << 7) || (!si->is_mobility)) {
if (si->is_mobility && (INREG(ai->regs, RADEON_BIOS_4_SCRATCH) & 4)) {
if (si->is_mobility && (INREG(ai->regs, RADEON_FP2_GEN_CNTL) & RADEON_FP2_FPON)) {
old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL);
old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL);
old_dac_cntl = INREG(regs, RADEON_DAC_CNTL);
found = (INREG(regs, RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) != 0;
old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);
old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);
old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);
found = (INREG(regs, RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) != 0;
old_radeon_gpiopad_a = INREG(regs, RADEON_GPIOPAD_A);
old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);
old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);
old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);
found = (INREG(regs, RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) != 0;
old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);
old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL);
old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);
old_tv_master_cntl = INREG(regs, RADEON_TV_MASTER_CNTL);
old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);
config_cntl = INREG(regs, RADEON_CONFIG_CNTL);
old_pre_dac_mux_cntl = INREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL);
value = INREG(regs, RADEON_TV_DAC_CNTL);
old_radeon_gpiopad_a = INREG(regs, RADEON_GPIOPAD_A);
value = INREG(regs, info->port);
old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);
old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);
old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL);
old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);
(void)INREG(regs, RADEON_TV_DAC_CNTL);
(void)INREG(regs, RADEON_TV_DAC_CNTL);
tmp = INREG(regs, RADEON_TV_DAC_CNTL);
value = INREG(regs, info->port);
values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG );
crtc_gen_cntl = INREG( regs, RADEON_CRTC_GEN_CNTL );
values->disp_tv_out_cntl = INREG( regs, RADEON_DISP_TV_OUT_CNTL );
crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A );
values->tv_dac_cntl = INREG( regs, RADEON_TV_DAC_CNTL );
values->tv_master_cntl = INREG( regs, RADEON_TV_MASTER_CNTL );
values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
while( (INREG( regs, RADEON_OV0_REG_LOAD_CNTL)
if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
INREG( di->regs, RADEON_RBBM_STATUS ),
INREG( di->regs, RADEON_CP_STAT ),
INREG( di->regs, RADEON_AIC_TLB_ADDR ),
INREG( di->regs, RADEON_AIC_TLB_DATA ));
int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
host_path_cntl = INREG( regs, RADEON_HOST_PATH_CNTL );
rbbm_soft_reset = INREG( regs, RADEON_RBBM_SOFT_RESET );
INREG( regs, RADEON_RBBM_SOFT_RESET);
INREG( regs, RADEON_RBBM_SOFT_RESET);
INREG( regs, RADEON_HOST_PATH_CNTL );
cur_read_ptr = INREG( regs, RADEON_CP_RB_RPTR );
INREG( regs, RADEON_CP_CSQ_CNTL );
INREG( di->regs, RADEON_CP_CSQ_CNTL );
SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));
INREG( regs, RADEON_CP_CSQ_CNTL );
if ((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > RADEON_CFG_ATI_REV_A13) {
if (INREG( regs, RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
INREG( regs, RADEON_CP_CSQ_CNTL );
((INREG( regs, RADEON_FP_VERT_STRETCH ) & RADEON_VERT_PANEL_SIZE)
(((INREG( regs, RADEON_FP_HORZ_STRETCH ) & RADEON_HORZ_PANEL_SIZE)
r = INREG( regs, RADEON_FP_CRTC_H_TOTAL_DISP );
r = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
r = INREG( regs, RADEON_FP_CRTC_V_TOTAL_DISP );
r = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
r = INREG( regs, RADEON_CRTC_H_TOTAL_DISP );
r = INREG( regs, RADEON_CRTC_H_SYNC_STRT_WID );
r = INREG( regs, RADEON_CRTC_V_TOTAL_DISP );
r = INREG( regs, RADEON_CRTC_V_SYNC_STRT_WID );
uint32 aper_size = INREG( regs, RADEON_CONFIG_APER_SIZE );
if (INREG( regs, RADEON_HOST_PATH_CNTL ) & RADEON_HDP_APER_CNTL )
tom = INREG( regs, RADEON_NB_TOM );
di->local_mem_size = INREG( regs, RADEON_CONFIG_MEMSIZE ) & RADEON_CONFIG_MEMSIZE_MASK;
tmp = INREG( regs, RADEON_MEM_CNTL );
uint32 mem_type = INREG( regs, RADEON_MEM_SDRAM_MODE_REG ) & RADEON_MEM_CFG_TYPE_MASK;
di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 );
si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL);
si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL);
INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
INREG( di->regs, RADEON_LVDS_PLL_CNTL ));
INREG( di->regs, RADEON_TMDS_PLL_CNTL ));
INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));
INREG( di->regs, RADEON_FP_GEN_CNTL ));
INREG( di->regs, RADEON_FP2_GEN_CNTL ));
INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi
full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);
int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);
cap_status = INREG(regs, RADEON_CAP_INT_STATUS);
cap_status &= INREG(regs, RADEON_CAP_INT_CNTL);
tom = INREG( di->regs, RADEON_NB_TOM );
uint32 aper0 = INREG( di->regs, RADEON_CONFIG_APER_0_BASE );
INREG( regs, RADEON_CLOCK_CNTL_DATA);
INREG( regs, RADEON_CRTC_GEN_CNTL);
save = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA );
res = INREG( regs, RADEON_CLOCK_CNTL_DATA );
INREG( regs, RADEON_VIPH_TIMEOUT_STAT) &
INREG( regs, RADEON_VIPH_REG_DATA);
tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
*buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff);
*(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff);
*(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff);
(INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT );
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK;
timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK ;
INREG( regs, RADEON_VIPH_REG_DATA );
*data = INREG( regs, RADEON_VIPH_REG_DATA );