HDAC_STREAM_BASE
return controller->Read8(HDAC_STREAM_BASE + offset + reg);
return controller->Read16(HDAC_STREAM_BASE + offset + reg);
return controller->Read32(HDAC_STREAM_BASE + offset + reg);
*(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
*(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
*(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE