ALC_MASTER_CFG
val = CSR_READ_4(sc, ALC_MASTER_CFG);
CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
CSR_WRITE_4(sc, ALC_MASTER_CFG,
CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
CSR_WRITE_4(sc, ALC_MASTER_CFG,
CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
CSR_WRITE_4(sc, ALC_MASTER_CFG,
CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
master = CSR_READ_4(sc, ALC_MASTER_CFG);
CSR_WRITE_4(sc, ALC_MASTER_CFG, master);
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&