AE_READ_4
eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
val = AE_READ_4(sc, AE_MAC_REG);
val = AE_READ_4(sc, AE_MAC_REG);
val = AE_READ_4(sc, AE_IDLE_REG);
val = AE_READ_4(sc, AE_MAC_REG);
val = AE_READ_4(sc, AE_IDLE_REG);
val = AE_READ_4(sc, AE_MAC_REG);
val = AE_READ_4(sc, AE_ISR_REG);
val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
val = AE_READ_4(sc, AE_MAC_REG);
rxcfg = AE_READ_4(sc, AE_MAC_REG);
if (AE_READ_4(sc, AE_IDLE_REG) == 0)
chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
if (AE_READ_4(sc, AE_IDLE_REG) == 0)
val = AE_READ_4(sc, AE_MASTER_REG);
val = AE_READ_4(sc, AE_ISR_REG);
val = AE_READ_4(sc, AE_MASTER_REG);
val = AE_READ_4(sc, AE_MAC_REG);
val = AE_READ_4(sc, AE_MDIO_REG);
aereg = AE_READ_4(sc, AE_MDIO_REG);
val = AE_READ_4(sc, AE_SPICTL_REG);
val = AE_READ_4(sc, AE_VPD_CAP_REG);
*word = AE_READ_4(sc, AE_VPD_DATA_REG);