headers/private/kernel/platform/efi/protocol/managed-network.h

73

efi_status (*Configure) (struct efi_managed_network_protocol* self,

src/add-ons/accelerants/intel_extreme/Pipes.h

42

void Configure(display_mode* mode);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1051

fPipe->Configure(target);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1342

fPipe->Configure(target);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1500

fPipe->Configure(target);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2125

fPipe->Configure(target);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2694

fPipe->Configure(target);

src/add-ons/accelerants/intel_extreme/mode.cpp

443

8. Configure and enable CPU planes (VGA or hires)

src/add-ons/accelerants/intel_extreme/mode.cpp

457

c. Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling

src/add-ons/accelerants/intel_extreme/mode.cpp

459

d. [DevCPT] Configure DPLL SEL to set the DPLL to transcoder mapping and enable DPLL to the

src/add-ons/accelerants/intel_extreme/mode.cpp

461

e. [DevCPT] Configure DPLL_CTL DPLL_HDMI_multipler.

src/add-ons/accelerants/intel_extreme/mode.cpp

462

f. Configure PCH transcoder timings, M/N/TU, and other transcoder settings (should match CPU settings).

src/add-ons/accelerants/intel_extreme/mode.cpp

463

g. [DevCPT] Configure and enable Transcoder DisplayPort Control if DisplayPort will be used

src/add-ons/kernel/bus_managers/ata/ATAChannel.cpp

237

if (device->Configure() != B_OK) {

src/add-ons/kernel/bus_managers/ata/ATAPrivate.h

205

virtual status_t Configure();

src/add-ons/kernel/bus_managers/ata/ATAPrivate.h

248

virtual status_t Configure();

src/servers/app/View.cpp

539

overlay->Configure(fBitmapSource, destination);

src/servers/app/drawing/Overlay.h

54

void Configure(const BRect& source, const BRect& destination);