CSR_READ_2
sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
status = CSR_READ_2(sc, XL_STATUS);
status = CSR_READ_2(sc, XL_STATUS);
status = CSR_READ_2(sc, XL_STATUS);
CSR_READ_2(sc, XL_W7_BM_PME);
status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
CSR_READ_2(sc, XL_W7_BM_PME);
if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
word = CSR_READ_2(sc, XL_W0_EE_DATA);
mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
u_int16_t status = CSR_READ_2(sc, XL_STATUS);
linkcfg = CSR_READ_2(sc, sc->alc_expcap +
cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
CSR_READ_2(sc, ALC_GPHY_CFG);
CSR_READ_2(sc, ALC_GPHY_CFG);
prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
idx = CSR_READ_2(sc_if->msk_softc,
CSR_READ_2((sc_if)->msk_softc, (reg))
CSR_READ_2((sc), GMAC_REG((port), (reg)))
return(CSR_READ_2(sc, PCN_IO16_RDP));
return(CSR_READ_2(sc, PCN_IO16_BDP));
CSR_READ_2(sc, PCN_IO16_RESET);
mcr = CSR_READ_2(sc, VTE_MCR0);
CSR_READ_2(sc, VTE_CNT_RX_DONE);
CSR_READ_2(sc, VTE_CNT_MECNT0);
CSR_READ_2(sc, VTE_CNT_MECNT1);
CSR_READ_2(sc, VTE_CNT_MECNT2);
CSR_READ_2(sc, VTE_CNT_MECNT3);
CSR_READ_2(sc, VTE_CNT_TX_DONE);
CSR_READ_2(sc, VTE_CNT_MECNT4);
CSR_READ_2(sc, VTE_CNT_PAUSE);
CSR_READ_2(sc, VTE_MECISR);
stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE);
value = CSR_READ_2(sc, VTE_CNT_MECNT0);
value = CSR_READ_2(sc, VTE_CNT_MECNT1);
value = CSR_READ_2(sc, VTE_CNT_MECNT2);
value = CSR_READ_2(sc, VTE_CNT_MECNT3);
stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE);
value = CSR_READ_2(sc, VTE_CNT_MECNT4);
value = CSR_READ_2(sc, VTE_CNT_PAUSE);
status = CSR_READ_2(sc, VTE_MISR);
status = CSR_READ_2(sc, VTE_MISR);
mdcsc = CSR_READ_2(sc, VTE_MDCSC);
mcr = CSR_READ_2(sc, VTE_MCR1);
if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0)
CSR_READ_2(sc, VTE_MISR);
if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
mcr = CSR_READ_2(sc, VTE_MCR0);
mcr = CSR_READ_2(sc, VTE_MCR0);
mcr = CSR_READ_2(sc, VTE_MCR0);
mcr = CSR_READ_2(sc, VTE_MCR0);
return (CSR_READ_2(sc, VTE_MMRD));
mcr = CSR_READ_2(sc, VTE_MCR0);
if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
CSR_READ_2(sc, VTE_MCR0);
mid = CSR_READ_2(sc, VTE_MID0L);
mid = CSR_READ_2(sc, VTE_MID0M);
mid = CSR_READ_2(sc, VTE_MID0H);
CSR_READ_2(sc, VTE_MACID));
macid = CSR_READ_2(sc, VTE_MACID_REV);
cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
return (CSR_READ_2(sc, rl8139_reg));
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
status = CSR_READ_2(sc, RL_ISR);
rval = CSR_READ_2(sc, re8139_reg);
status = CSR_READ_2(sc, RL_ISR);
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
status = CSR_READ_2(sc, RL_ISR);
rxfilt = CSR_READ_2(sc, RxMacControl);
rxfilt = CSR_READ_2(sc, RxMacControl);
((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
return(CSR_READ_2(sc, reg));
status = CSR_READ_2(sc, VR_ISR);
status = CSR_READ_2(sc, VR_ISR);
status = CSR_READ_2(sc, VR_ISR);
status = CSR_READ_2(sc, VR_ISR);
return (CSR_READ_2(sc, VR_MIIDATA));
#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
word = CSR_READ_2(sc, VGE_EERDDAT);
rval = CSR_READ_2(sc, VGE_MIIDATA);
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
id = CSR_READ_2(sc, AN_TX_CMP_FID(sc->mpi350));
id = CSR_READ_2(sc, AN_TX_CMP_FID(sc->mpi350));
status = CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350));
if (CSR_READ_2(sc, AN_LINKSTAT(sc->mpi350))
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY) {
if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_CMD)
reply->an_resp0 = CSR_READ_2(sc, AN_RESP0(sc->mpi350));
reply->an_resp1 = CSR_READ_2(sc, AN_RESP1(sc->mpi350));
reply->an_resp2 = CSR_READ_2(sc, AN_RESP2(sc->mpi350));
reply->an_status = CSR_READ_2(sc, AN_STATUS(sc->mpi350));
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY)
if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_CMD)
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) == cmd)
CSR_READ_2(sc, AN_RESP0(sc->mpi350));
CSR_READ_2(sc, AN_RESP1(sc->mpi350));
CSR_READ_2(sc, AN_RESP2(sc->mpi350));
s = CSR_READ_2(sc, AN_STATUS(sc->mpi350));
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY)
len = CSR_READ_2(sc, AN_DATA1);
*ptr++ = CSR_READ_2(sc, AN_DATA1);
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350))
if (!(CSR_READ_2(sc, offreg) & (AN_OFF_BUSY|AN_OFF_ERR)))
*ptr++ = CSR_READ_2(sc, AN_DATA1);
if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_ALLOC)
*id = CSR_READ_2(sc, AN_ALLOC_FID);
if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY) {
statword = CSR_READ_2(sc, AN_COMMAND(sc->mpi350));
rchar = CSR_READ_2(sc, AN_SW1(sc->mpi350));
pollbusy = CSR_READ_2(sc, AN_SW0(sc->mpi350));
echo = CSR_READ_2(sc, AN_SW1(sc->mpi350));
id = CSR_READ_2(sc, AN_RX_FID);
return CSR_READ_2(sc, data_reg);
ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN);
ret |= CSR_READ_2(sc, BWI_MOBJ_DATA);
CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */
if (CSR_READ_2(sc, 0x50e) & 0x80)
if (CSR_READ_2(sc, 0x50e) & 0x400)
if ((CSR_READ_2(sc, 0x690) & 0x100) == 0)
return CSR_READ_2(sc, BWI_PHY_DATA);
val = CSR_READ_2(sc, BWI_PHYINFO);
ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
CSR_READ_2(sc, BWI_BBP_ATTEN);
chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
return CSR_READ_2(sc, BWI_RF_DATA_LO);
val = CSR_READ_2(sc, BWI_RF_DATA_HI);
val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
return CSR_READ_2(sc, ofs + BWI_SPROM_START);
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))