CSR_READ_1
while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
CSR_READ_1(sc, XL_W4_BADSSD);
macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
CSR_READ_1(sc, FXP_CSR_PMDR));
tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
} while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0);
if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
uint8_t statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
CSR_READ_1((sc_if)->msk_softc, (reg))
while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
if ((CSR_READ_1(sc, RL_COMMAND) &
v = CSR_READ_1(sc, sc->rl_cfg1);
v = CSR_READ_1(sc, sc->rl_cfg3);
v = CSR_READ_1(sc, sc->rl_cfg5);
v = CSR_READ_1(sc, sc->rl_cfg3);
v = CSR_READ_1(sc, sc->rl_cfg5);
CSR_READ_1(sc, RL_EECMD) | x)
CSR_READ_1(sc, RL_EECMD) & ~x)
if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
val = CSR_READ_1(sc, RL_MII);
return (CSR_READ_1(sc, RL_MEDIASTAT));
if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
cfg = CSR_READ_1(sc, RL_CFG2);
cfg = CSR_READ_1(sc, RL_CFG2);
cfg = CSR_READ_1(sc, sc->rl_cfg1);
cfg = CSR_READ_1(sc, sc->rl_cfg5);
eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
CSR_READ_1(sc, RL_GPIO) | 0x01);
CSR_READ_1(sc, RL_GPIO) & ~0x01);
CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
CSR_READ_1(sc, RL_EECMD) | x)
CSR_READ_1(sc, RL_EECMD) & ~x)
if ((CSR_READ_1(sc, sc->rl_txstart) &
if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
CSR_READ_1(sc, RL_GPIO) | 0x01);
if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
CSR_READ_1(sc, RL_GPIO) & ~0x01);
v = CSR_READ_1(sc, sc->rl_cfg1);
v = CSR_READ_1(sc, sc->rl_cfg3);
v = CSR_READ_1(sc, sc->rl_cfg5);
CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
v = CSR_READ_1(sc, sc->rl_cfg3);
v = CSR_READ_1(sc, sc->rl_cfg5);
if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
rval = CSR_READ_1(sc, RL_GMEDIASTAT);
rval = CSR_READ_1(sc, RL_MEDIASTAT);
if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
return(CSR_READ_1(sc, reg));
cmd = CSR_READ_1(sc, VR_CR0);
cmd = CSR_READ_1(sc, VR_CR0);
cmd = CSR_READ_1(sc, VR_CR0);
cmd = CSR_READ_1(sc, VR_CR0);
cmd = CSR_READ_1(sc, VR_CR0);
cmd = CSR_READ_1(sc, VR_CR0);
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
v = CSR_READ_1(sc, VR_STICKHW);
v = CSR_READ_1(sc, VR_STICKHW);
v = CSR_READ_1(sc, VR_STICKHW);
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
cr0 = CSR_READ_1(sc, VR_CR0);
cr1 = CSR_READ_1(sc, VR_CR1);
fc = CSR_READ_1(sc, VR_FLOWCR1);
fc = CSR_READ_1(sc, VR_MISC_CR0);
if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
rxfilt = CSR_READ_1(sc, VR_RXCFG);
if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)
eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
physts = CSR_READ_1(sc, VGE_PHYSTS0);
if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE);
CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR);
if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0)
CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &
CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH);
if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0)
CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI);
intctl = CSR_READ_1(sc, VGE_INTCTL1);
val = CSR_READ_1(sc, VGE_PWRSTAT);
val = CSR_READ_1(sc, VGE_PWRSTAT);
val = CSR_READ_1(sc, VGE_PWRSTAT);
val = CSR_READ_1(sc, VGE_PWRSTAT);
dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
cfg = CSR_READ_1(sc, VGE_RXCFG);
rxcfg = CSR_READ_1(sc, VGE_RXCTL);
if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
*ptr2 = CSR_READ_1(sc, AN_DATA1);
*ptr2 = CSR_READ_1(sc, AN_DATA1);
*datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA);