src/add-ons/accelerants/matrox/engine/mga_crtc2.c

101

CR2W(HSYNC, ((((tv_mode.timing.h_sync_end - 8) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

103

CR2W(VPARAM, ((((tv_mode.timing.v_display - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

105

CR2W(VSYNC, ((((tv_mode.timing.v_sync_end - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

110

CR2W(PRELOAD, ((((tv_mode.timing.v_sync_start - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

116

CR2W(CTL, ((CR2R(CTL) & ~0x02000000) | 0x00001000));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

131

CR2W(CTL, (CR2R(CTL) | 0x02000000));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

136

CR2W(MISC, temp);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

149

CR2W(CTL,(CR2R(CTL)&0xFF10077F)|(mode<<21));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

171

CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

177

CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

196

CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

202

CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

290

CR2W(OFFSET,offset);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

308

CR2W(STARTADD0, (startadd + si->fbc.bytes_per_row));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

310

CR2W(STARTADD1, startadd);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

316

CR2W(STARTADD0, startadd);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

32

CR2W(DATACTL, (CR2R(DATACTL) & ~0x00000010));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

35

CR2W(CTL, (CR2R(CTL) & ~0x02001000));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

38

CR2W(HPARAM, ((((target.timing.h_display - 8) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

40

CR2W(HSYNC, ((((target.timing.h_sync_end - 8) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

42

CR2W(VPARAM, ((((target.timing.v_display - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

44

CR2W(VSYNC, ((((target.timing.v_sync_end - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

49

CR2W(PRELOAD, ((((target.timing.v_sync_start - 1) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

55

CR2W(MISC, temp);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

80

CR2W(DATACTL, (CR2R(DATACTL) & ~0x00000010));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

86

CR2W(DATACTL, (CR2R(DATACTL) | 0x00000010));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

99

CR2W(HPARAM, ((((tv_mode.timing.h_display - 8) & 0x0fff) << 16) |

src/add-ons/accelerants/matrox/engine/mga_general.c

598

CR2W(DATACTL,0x00000000);

src/add-ons/accelerants/matrox/engine/mga_general.c

755

CR2W(DATACTL,0x00000000);

src/add-ons/accelerants/matrox/engine/mga_general.c

815

if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0xffe00779)|0xD0000002);

src/add-ons/accelerants/matrox/engine/mga_general.c

827

if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0x2fe00779)|0x4|(0x1<<20));

src/add-ons/accelerants/matrox/engine/mga_general.c

845

CR2W(CTL,(CR2R(CTL)&0x2de00779)|0x6|(0x0<<20));

src/add-ons/accelerants/matrox/engine/mga_general.c

863

CR2W(CTL,(CR2R(CTL)&0x2de00779)|0x6|(0x1<<20));

src/add-ons/accelerants/matrox/engine/mga_maven.c

280

CR2W(CTL, (CR2R(CTL) | 0x08)); /* disable the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

281

CR2W(CTL, (CR2R(CTL) | 0x06)); /* select the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

297

CR2W(CTL, (CR2R(CTL) & ~0x08)); /* enable the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

479

CR2W(CTL, (CR2R(CTL) | 0x06)); /* select the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

518

CR2W(CTL, (CR2R(CTL) | 0x08)); /* disable the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

536

CR2W(CTL, (CR2R(CTL) & ~0x08)); /* enable the VIDPLL */

src/add-ons/accelerants/matrox/engine/mga_maven.c

555

CR2W(CTL, (CR2R(CTL) & ~0x08)); /* enable the VIDPLL */