CPU
8. Configure and enable CPU planes (VGA or hires)
ii. Enable CPU FDI Transmitter and PCH FDI Receiver with Training Pattern 1 enabled.
v. Enable training pattern 2 on CPU FDI Transmitter and PCH FDI Receiver
viii. Enable normal pixel output on CPU FDI Transmitter and PCH FDI Receiver
f. Configure PCH transcoder timings, M/N/TU, and other transcoder settings (should match CPU settings).
if (!source->PerCPU() || source->CPU() == 0)
virtual int32 CPU() const;
virtual int32 CPU() const;
virtual int32 CPU() const;
Model::CPU::CPU()
for (int32 i = 0; CPU* cpu = CPUAt(i); i++)
Model::CPU::SetIdleTime(nanotime_t time)
CPU* cpu = new(std::nothrow) CPU;
class Model::CPU {
CPU();
class CPU;
Model::CPU*
Model::CPU::IdleTime() const
inline CPU* CPUAt(int32 index) const;
CPU::CPU(int32 num)
CPU::~CPU()
CPU::Quit()
CPU::_Run()
CPU::_Run(void* self)
CPU* cpu = (CPU*)self;
CPU* cpu = (CPU*)tls_get(sCPUIndexSlot);
CPU* cpu = (CPU*)tls_get(sCPUIndexSlot);
sCPU[i] = new CPU(i);
CPU(int32 num);
~CPU();
static CPU* sCPU[kMaxCPUCount];
CPUStore *CPU() const { return &fStores[smp_get_current_cpu()]; }
void *object = BaseDepot::ObtainFromStore(CPU());
if (!BaseDepot::ReturnToStore(CPU(), object))