CACHE_LINE_SIZE
#define CACHE_LINE_ALIGN __attribute__((aligned(CACHE_LINE_SIZE)))
} __aligned(CACHE_LINE_SIZE);
} __aligned(CACHE_LINE_SIZE);
int isc_nfl __aligned(CACHE_LINE_SIZE);
volatile uint64_t state __aligned(CACHE_LINE_SIZE);
int size __aligned(CACHE_LINE_SIZE);
] __aligned(CACHE_LINE_SIZE);
#if (CACHE_LINE_SIZE < 128)
__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long)))));
#define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *))
#define CACHE_PTR_NEXT(ptr) ((void *)(roundup2((intptr_t)ptr, CACHE_LINE_SIZE)))
next = (cidx + CACHE_LINE_SIZE) & (ntxd - 1);
bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
} __aligned(CACHE_LINE_SIZE);
uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
} __aligned(CACHE_LINE_SIZE);
struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
} __aligned(CACHE_LINE_SIZE);
node->data.package.cache_line_size = CACHE_LINE_SIZE;
node->data.package.cache_line_size = CACHE_LINE_SIZE;
node->data.package.cache_line_size = CACHE_LINE_SIZE;
node->data.package.cache_line_size = CACHE_LINE_SIZE;
node->data.package.cache_line_size = CACHE_LINE_SIZE;
node->data.package.cache_line_size = CACHE_LINE_SIZE;
size_t needed = ROUNDUP(sizeof(user_thread), CACHE_LINE_SIZE);