wrmsr
wrmsr ; \
wrmsr ; \
wrmsr ; \
struct nvmm_x86_exit_wrmsr wrmsr;
if (exit->u.wrmsr.msr == MSR_EFER) {
if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) {
if ((vmcb->state.efer ^ exit->u.wrmsr.val) &
vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME;
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip;
wrmsr(MSR_STAR, svm_global_hstate.star);
wrmsr(MSR_LSTAR, svm_global_hstate.lstar);
wrmsr(MSR_CSTAR, svm_global_hstate.cstar);
wrmsr(MSR_SFMASK, svm_global_hstate.sfmask);
wrmsr(MSR_FSBASE, cpudata->hstate.fsbase);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_VM_CR, msr & ~VM_CR_SVMED);
wrmsr(MSR_VM_HSAVE_PA, 0);
wrmsr(MSR_EFER, msr);
wrmsr(MSR_VM_HSAVE_PA, hsave[os_curcpu_number()].pa);
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (exit->u.wrmsr.msr == MSR_CR_PAT) {
val = exit->u.wrmsr.val;
if (exit->u.wrmsr.msr == MSR_MISC_ENABLE) {
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = rip + inslen;
wrmsr(MSR_STAR, vmx_global_hstate.star);
wrmsr(MSR_LSTAR, vmx_global_hstate.lstar);
wrmsr(MSR_CSTAR, vmx_global_hstate.cstar);
wrmsr(MSR_SFMASK, vmx_global_hstate.sfmask);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_IA32_FEATURE_CONTROL, msr |
void wrmsr(u_int msr, uint64_t newval);
void wrmsr(u_int msr, uint64_t newval);
wrmsr ; \
wrmsr ; \
wrmsr ; \
struct nvmm_x86_exit_wrmsr wrmsr;
if (exit->u.wrmsr.msr == MSR_EFER) {
if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) {
if ((vmcb->state.efer ^ exit->u.wrmsr.val) &
vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME;
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip;
wrmsr(MSR_STAR, svm_global_hstate.star);
wrmsr(MSR_LSTAR, svm_global_hstate.lstar);
wrmsr(MSR_CSTAR, svm_global_hstate.cstar);
wrmsr(MSR_SFMASK, svm_global_hstate.sfmask);
wrmsr(MSR_FSBASE, cpudata->hstate.fsbase);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_VM_CR, msr & ~VM_CR_SVMED);
wrmsr(MSR_VM_HSAVE_PA, 0);
wrmsr(MSR_EFER, msr);
wrmsr(MSR_VM_HSAVE_PA, hsave[os_curcpu_number()].pa);
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (exit->u.wrmsr.msr == MSR_CR_PAT) {
val = exit->u.wrmsr.val;
if (exit->u.wrmsr.msr == MSR_MISC_ENABLE) {
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = rip + inslen;
wrmsr(MSR_STAR, vmx_global_hstate.star);
wrmsr(MSR_LSTAR, vmx_global_hstate.lstar);
wrmsr(MSR_CSTAR, vmx_global_hstate.cstar);
wrmsr(MSR_SFMASK, vmx_global_hstate.sfmask);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_IA32_FEATURE_CONTROL, msr |