x86_write_msr
x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&t->arch_info);
x86_write_msr(IA32_MSR_HV_SIMP, msr);
x86_write_msr(IA32_MSR_HV_SIEFP, msr);
x86_write_msr(IA32_MSR_HV_SINT0 + VMBUS_SINT_MESSAGE, msr);
x86_write_msr(IA32_MSR_HV_SINT0 + VMBUS_SINT_TIMER, msr);
x86_write_msr(IA32_MSR_HV_SCONTROL, msr);
x86_write_msr(IA32_MSR_HV_SCONTROL, msr);
x86_write_msr(IA32_MSR_HV_SIMP, msr);
x86_write_msr(IA32_MSR_HV_SIEFP, msr);
x86_write_msr(IA32_MSR_HV_SINT0 + VMBUS_SINT_MESSAGE, msr);
x86_write_msr(IA32_MSR_HV_SINT0 + VMBUS_SINT_TIMER, msr);
x86_write_msr(IA32_MSR_HV_EOM, 0);
x86_write_msr(IA32_MSR_HV_GUEST_OS_ID, IA32_MSR_HV_GUEST_OS_ID_FREEBSD);
x86_write_msr(IA32_MSR_HV_HYPERCALL, msr);
x86_write_msr(IA32_MSR_HV_HYPERCALL, msr);
x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType);
x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType | IA32_MTRR_ENABLE);
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0);
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index,
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index,
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0);
x86_write_msr(MSR_AMD_CPPC_ENABLE, 1);
x86_write_msr(MSR_AMD_CPPC_REQ, request & 0xffffffff);
x86_write_msr(IA32_MSR_PERF_CTL, pstate << 8);
x86_write_msr(IA32_MSR_HWP_INTERRUPT, 0);
x86_write_msr(IA32_MSR_PM_ENABLE, 1);
x86_write_msr(IA32_MSR_ENERGY_PERF_BIAS, perfBias);
x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest
x86_write_msr(IA32_MSR_HWP_REQUEST_PKG, hwpRequest);
x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest);
x86_write_msr(IA32_MSR_APIC_ERROR_STATUS, config);
x86_write_msr(IA32_MSR_APIC_INTR_COMMAND, command);
x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop);
x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR);
x86_write_msr(IA32_MSR_SYSENTER_ESP, 0);
x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_sysenter);
x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 57));
x86_write_msr(MSR_F10H_DE_CFG, x86_read_msr(MSR_F10H_DE_CFG) | (1 << 9));
x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | 1);
x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 15));
x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | (1 << 13));
x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | (1 << 4));
x86_write_msr(0xc0011028, x86_read_msr(0xc0011028) | (1 << 4));
x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop);
x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR);
x86_write_msr(IA32_MSR_SYSENTER_ESP, 0);
x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_64_sysenter32_entry);
x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
x86_write_msr(IA32_MSR_FMASK, X86_EFLAGS_INTERRUPT | X86_EFLAGS_DIRECTION
x86_write_msr(IA32_MSR_LSTAR, (addr_t)x86_64_syscall_entry);
x86_write_msr(IA32_MSR_CSTAR, (addr_t)x86_64_syscall32_entry);
x86_write_msr(IA32_MSR_STAR, ((uint64)(USER32_CODE_SELECTOR) << 48)
x86_write_msr(IA32_MSR_FS_BASE, thread->user_local_storage);
x86_write_msr(IA32_MSR_KERNEL_GS_BASE, thread->arch_info.user_gs_base);
x86_write_msr(IA32_MSR_KERNEL_GS_BASE, base);
x86_write_msr(IA32_MSR_APIC_EOI, 0);
x86_write_msr(IA32_MSR_APIC_LVT_LINT0, APIC_LVT_MASKED);
x86_write_msr(IA32_MSR_APIC_LVT_LINT1, APIC_LVT_MASKED);
x86_write_msr(IA32_MSR_APIC_SPURIOUS_INTR_VECTOR, config);
x86_write_msr(IA32_MSR_APIC_INTR_COMMAND, command);
x86_write_msr(IA32_MSR_APIC_LVT_TIMER, config);
x86_write_msr(IA32_MSR_APIC_LVT_ERROR, config);
x86_write_msr(IA32_MSR_APIC_INITIAL_TIMER_COUNT, config);
x86_write_msr(IA32_MSR_APIC_TIMER_DIVIDE_CONFIG, config);
x86_write_msr(IA32_MSR_APIC_BASE, apic_base
x86_write_msr(IA32_MSR_APIC_TASK_PRIORITY, config);
x86_write_msr(IA32_MSR_UCODE_REV, 0);
x86_write_msr(IA32_MSR_UCODE_WRITE, data);
x86_write_msr(MSR_K8_UCODE_UPDATE, data);
x86_write_msr(IA32_MSR_TSC, 0);
x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT);
x86_write_msr(IA32_MSR_TSC_AUX, cpu);
x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE);
x86_write_msr(IA32_MSR_PAT, value);
x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&unsetThread);
x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)