src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

107

write32(targetRegister, value);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

110

write32(targetRegister, value | FDI_TX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

126

write32(targetRegister, read32(targetRegister) & ~FDI_TX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

154

write32(targetRegister, value | FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

167

write32(targetRegister, value & ~FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

202

write32(targetRegister, value);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

205

write32(targetRegister, value | FDI_RX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

216

write32(targetRegister, read32(targetRegister) & ~FDI_RX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

227

write32(targetRegister, (read32(targetRegister) & ~FDI_RX_CLOCK_MASK)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

301

write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

303

write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

306

write32(txControl, (read32(txControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

309

write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_PATTERN_MASK_CPT) | FDI_LINK_TRAIN_PATTERN_1_CPT);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

311

write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

337

write32(FDI_RX_TUSIZE1(fPipeIndex), FDI_RX_TRANS_UNIT_MASK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

338

write32(FDI_RX_TUSIZE2(fPipeIndex), FDI_RX_TRANS_UNIT_MASK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

385

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

395

write32(rxControl, tmp | FDI_RX_ENHANCE_FRAME_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

403

write32(rxControl, read32(rxControl)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

423

write32(FDI_RX_IMR(fPipeIndex), tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

432

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

438

write32(rxControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

443

write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

444

write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

447

write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

448

write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

462

write32(iirControl, tmp | FDI_RX_BIT_LOCK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

476

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

481

write32(rxControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

492

write32(iirControl, tmp | FDI_RX_SYMBOL_LOCK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

518

write32(imrControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

530

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

532

write32(FDI_RX_MISC(fPipeIndex),

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

543

write32(rxControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

554

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

565

write32(iirControl, tmp | FDI_RX_BIT_LOCK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

587

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

597

write32(rxControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

606

write32(txControl, tmp);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

618

write32(iirControl, tmp | FDI_RX_SYMBOL_LOCK);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

64

write32(targetRegister, value | FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

667

write32(txControl, buffer);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

669

write32(FDI_RX_MISC(fPipeIndex), FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

680

write32(txControl, buffer | FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

682

write32(rxControl, read32(rxControl) | FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

694

write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

696

write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

714

write32(rxControl, read32(rxControl)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

718

write32(txControl, read32(txControl) | (0x3 << 8));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

77

write32(targetRegister, value & ~FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

101

write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, 0);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

109

write32(targetRegister, (read32(targetRegister) & ~PANEL_FITTER_ENABLED)

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

62

write32(fRegisterBase + PCH_PANEL_FITTER_CONTROL, fitCtl);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

91

write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, (timing.h_display << 16) | timing.v_display);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

147

write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

154

write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

168

write32(INTEL_TRANSCODER_A_HTOTAL + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

171

write32(INTEL_TRANSCODER_A_HBLANK + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

174

write32(INTEL_TRANSCODER_A_HSYNC + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

178

write32(INTEL_TRANSCODER_A_VTOTAL + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

181

write32(INTEL_TRANSCODER_A_VBLANK + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

184

write32(INTEL_TRANSCODER_A_VSYNC + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

190

write32(INTEL_TRANSCODER_A_POS + fPipeOffset, 0);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

191

write32(INTEL_TRANSCODER_A_IMAGE_SIZE + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

270

write32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

271

write32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

287

write32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset, ret_m);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

289

write32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

318

write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

323

write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

337

write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

364

write32(INTEL_DISPLAY_A_HTOTAL + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

367

write32(INTEL_DISPLAY_A_HBLANK + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

370

write32(INTEL_DISPLAY_A_HSYNC + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

374

write32(INTEL_DISPLAY_A_VTOTAL + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

377

write32(INTEL_DISPLAY_A_VBLANK + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

380

write32(INTEL_DISPLAY_A_VSYNC + fPipeOffset,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

419

write32(pllControl, read32(pllControl) & ~DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

42

write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

427

write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

433

write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

437

write32(pllDivisorB, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

442

write32(pllDivisorA, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

448

write32(pllDivisorB, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

45

write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

49

write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

503

write32(pllControl, pll & ~DISPLAY_PLL_ENABLED & ~DISPLAY_PLL_NO_VGA_CONTROL);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

508

write32(pllControl, pll);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

52

write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

545

write32(SNB_DPLL_SEL, pllSel);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

589

write32(SKL_DPLL_CTRL1, portSel | (1 << (*pllSel * 6)));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

591

write32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

595

write32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8,

src/add-ons/accelerants/intel_extreme/Pipes.cpp

636

write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

638

write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

643

write32(INTEL_DISPLAY_A_PIPE_WATERMARK, 0x0783818);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

645

write32(INTEL_DISPLAY_B_PIPE_WATERMARK, 0x0783818);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

648

write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

653

write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1056

write32(_PortRegister(), (read32(_PortRegister())

src/add-ons/accelerants/intel_extreme/Ports.cpp

1087

write32(panelControl, read32(panelControl) | PANEL_REGISTER_UNLOCK);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1226

write32(panelControl,

src/add-ons/accelerants/intel_extreme/Ports.cpp

1332

write32(_PortRegister(), lvds);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1352

write32(panelControl,

src/add-ons/accelerants/intel_extreme/Ports.cpp

1375

write32(INTEL_PANEL_FIT_CONTROL, panelFitterControl);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1384

write32(INTEL_PANEL_FIT_CONTROL, panelFitterControl);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1394

write32(INTEL_PANEL_FIT_CONTROL, 0x4);

src/add-ons/accelerants/intel_extreme/Ports.cpp

177

write32(portRegister, portState | PORT_TRANS_B_SEL_CPT);

src/add-ons/accelerants/intel_extreme/Ports.cpp

180

write32(portRegister, portState | PORT_TRANS_C_SEL_CPT);

src/add-ons/accelerants/intel_extreme/Ports.cpp

183

write32(portRegister, portState | PORT_TRANS_A_SEL_CPT);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1874

write32(INTEL_PIPE_A_DATA_M + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1875

write32(INTEL_PIPE_A_DATA_N + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

189

write32(portRegister, portState & ~DISPLAY_MONITOR_PIPE_B);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1891

write32(INTEL_PIPE_A_LINK_M + fPipeOffset, ret_m);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1893

write32(INTEL_PIPE_A_LINK_N + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

191

write32(portRegister, portState | DISPLAY_MONITOR_PIPE_B);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1983

write32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset, ret_m | INTEL_TRANSCODER_MN_TU_SIZE_MASK);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1984

write32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2000

write32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset, ret_m);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2002

write32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2249

write32(portRegister,

src/add-ons/accelerants/intel_extreme/Ports.cpp

2576

write32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2577

write32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2593

write32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset, ret_m);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2595

write32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset, ret_n);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2746

write32(TGL_DPCLKA_CFGCR0, config);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2748

write32(TGL_DPCLKA_CFGCR0, config);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2753

write32(TGL_DPCLKA_CFGCR0, config);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2755

write32(TGL_DPCLKA_CFGCR0, config);

src/add-ons/accelerants/intel_extreme/Ports.cpp

411

write32(ioRegister, value);

src/add-ons/accelerants/intel_extreme/Ports.cpp

606

write32(ICL_PWR_WELL_CTL_AUX2, value | HSW_PWR_WELL_CTL_REQ(0));

src/add-ons/accelerants/intel_extreme/Ports.cpp

905

write32(channelData[index], data);

src/add-ons/accelerants/intel_extreme/Ports.cpp

907

write32(channelControl, sendControl);

src/add-ons/accelerants/intel_extreme/Ports.cpp

915

write32(channelControl, status | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_TIMEOUT_ERROR

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

306

write32(DPLL_ENABLE, read32(DPLL_ENABLE) & ~TGL_DPLL_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

311

write32(DPLL_ENABLE, read32(DPLL_ENABLE) | TGL_DPLL_POWER_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

318

write32(DPLL_SPREAD_SPECTRUM, read32(DPLL_SPREAD_SPECTRUM) & ~TGL_DPLL_SSC_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

321

write32(DPLL_CFGCR0, dco_reg);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

324

write32(DPLL_CFGCR1, dividers);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

335

write32(DPLL_ENABLE, read32(DPLL_ENABLE) | TGL_DPLL_ENABLE);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

276

write32(INTEL_DSPCLK_GATE_D,

src/add-ons/accelerants/intel_extreme/accelerant.cpp

280

write32(INTEL_GEN9_CLKGATE_DIS_4,

src/add-ons/accelerants/intel_extreme/accelerant.cpp

284

write32(INTEL_GMBUS0, 0); //reset, idle

src/add-ons/accelerants/intel_extreme/accelerant.cpp

285

write32(INTEL_GMBUS4, 0); //block interrupts

src/add-ons/accelerants/intel_extreme/cursor.cpp

108

write32(INTEL_CURSOR_CONTROL, (isVisible ? CURSOR_ENABLED : 0)

src/add-ons/accelerants/intel_extreme/cursor.cpp

110

write32(INTEL_CURSOR_BASE,

src/add-ons/accelerants/intel_extreme/cursor.cpp

23

write32(INTEL_CURSOR_CONTROL, 0);

src/add-ons/accelerants/intel_extreme/cursor.cpp

48

write32(INTEL_CURSOR_PALETTE + 0, 0x00ffffff);

src/add-ons/accelerants/intel_extreme/cursor.cpp

49

write32(INTEL_CURSOR_PALETTE + 4, 0);

src/add-ons/accelerants/intel_extreme/cursor.cpp

53

write32(INTEL_CURSOR_CONTROL,

src/add-ons/accelerants/intel_extreme/cursor.cpp

55

write32(INTEL_CURSOR_SIZE, height << 12 | width);

src/add-ons/accelerants/intel_extreme/cursor.cpp

57

write32(INTEL_CURSOR_BASE,

src/add-ons/accelerants/intel_extreme/cursor.cpp

98

write32(INTEL_CURSOR_POSITION, (y << 16) | x);

src/add-ons/accelerants/intel_extreme/dpms.cpp

101

write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/dpms.cpp

109

write32(INTEL_DISPLAY_B_PLL, pll);

src/add-ons/accelerants/intel_extreme/dpms.cpp

112

write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/dpms.cpp

115

write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/dpms.cpp

142

write32(INTEL_ANALOG_PORT, (read32(INTEL_ANALOG_PORT)

src/add-ons/accelerants/intel_extreme/dpms.cpp

150

write32(INTEL_DIGITAL_PORT_B, (read32(INTEL_DIGITAL_PORT_B)

src/add-ons/accelerants/intel_extreme/dpms.cpp

160

write32(INTEL_DISPLAY_A_PLL, read32(INTEL_DISPLAY_A_PLL)

src/add-ons/accelerants/intel_extreme/dpms.cpp

162

write32(INTEL_DISPLAY_B_PLL, read32(INTEL_DISPLAY_B_PLL)

src/add-ons/accelerants/intel_extreme/dpms.cpp

61

write32(controlRegister, control | PANEL_CONTROL_POWER_TARGET_ON

src/add-ons/accelerants/intel_extreme/dpms.cpp

72

write32(controlRegister, (control & ~PANEL_CONTROL_POWER_TARGET_ON)

src/add-ons/accelerants/intel_extreme/dpms.cpp

95

write32(INTEL_DISPLAY_A_PLL, pll);

src/add-ons/accelerants/intel_extreme/dpms.cpp

98

write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/engine.cpp

161

write32(ringBuffer.register_base + RING_BUFFER_CONTROL, 0);

src/add-ons/accelerants/intel_extreme/engine.cpp

181

write32(ring + RING_BUFFER_TAIL, 0);

src/add-ons/accelerants/intel_extreme/engine.cpp

182

write32(ring + RING_BUFFER_START, ringBuffer.offset);

src/add-ons/accelerants/intel_extreme/engine.cpp

183

write32(ring + RING_BUFFER_CONTROL,

src/add-ons/accelerants/intel_extreme/engine.cpp

54

write32(fRingBuffer.register_base + RING_BUFFER_TAIL, fRingBuffer.position);

src/add-ons/accelerants/intel_extreme/mode.cpp

145

write32(INTEL_DISPLAY_A_OFFSET_HAS + offset,

src/add-ons/accelerants/intel_extreme/mode.cpp

150

write32(INTEL_DISPLAY_A_BASE + offset,

src/add-ons/accelerants/intel_extreme/mode.cpp

155

write32(INTEL_DISPLAY_A_SURFACE + offset, sharedInfo.frame_buffer_offset);

src/add-ons/accelerants/intel_extreme/mode.cpp

158

write32(INTEL_DISPLAY_A_BASE + offset, sharedInfo.frame_buffer_offset

src/add-ons/accelerants/intel_extreme/mode.cpp

475

write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED);

src/add-ons/accelerants/intel_extreme/mode.cpp

505

write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow >> 6);

src/add-ons/accelerants/intel_extreme/mode.cpp

506

write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow >> 6);

src/add-ons/accelerants/intel_extreme/mode.cpp

508

write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow);

src/add-ons/accelerants/intel_extreme/mode.cpp

509

write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow);

src/add-ons/accelerants/intel_extreme/mode.cpp

627

write32(intel_get_backlight_register(false), duty);

src/add-ons/accelerants/intel_extreme/mode.cpp

634

write32(intel_get_backlight_register(false), duty | (period << 16));

src/add-ons/accelerants/intel_extreme/mode.cpp

675

write32(intel_get_backlight_register(false), (duty & mask) | (tmp & ~mask));

src/add-ons/accelerants/intel_extreme/mode.cpp

811

write32(INTEL_DISPLAY_A_PALETTE + first * sizeof(uint32), color);

src/add-ons/accelerants/intel_extreme/mode.cpp

812

write32(INTEL_DISPLAY_B_PALETTE + first * sizeof(uint32), color);

src/add-ons/accelerants/intel_extreme/pll.cpp

522

write32(PCH_DREF_CONTROL, newRef);

src/add-ons/accelerants/intel_extreme/pll.cpp

539

write32(PCH_DREF_CONTROL, newRef);

src/add-ons/accelerants/intel_extreme/pll.cpp

548

write32(PCH_DREF_CONTROL, newRef);

src/add-ons/accelerants/intel_extreme/pll.cpp

559

write32(PCH_DREF_CONTROL, newRef);

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

659

write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT),

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

831

write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL,

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

132

write32(bus->registers + PCH_IC_CON,

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

134

write32(bus->registers + PCH_IC_TAR, slaveAddress);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

136

write32(bus->registers + PCH_IC_INTR_MASK, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

142

write32(bus->registers + PCH_IC_INTR_MASK, PCH_IC_INTR_STAT_TX_EMPTY);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

163

write32(bus->registers + PCH_IC_DATA_CMD, cmd);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

185

write32(bus->registers + PCH_IC_DATA_CMD, cmd);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

194

write32(bus->registers + PCH_IC_INTR_MASK,

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

235

write32(bus->registers + PCH_IC_INTR_MASK,

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

30

write32(bus->registers + PCH_IC_ENABLE, status);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

428

write32(bus->registers + PCH_SUP_RESETS, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

429

write32(bus->registers + PCH_SUP_RESETS, PCH_SUP_RESETS_FUNC | PCH_SUP_RESETS_IDMA);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

448

write32(bus->registers + PCH_IC_SS_SCL_HCNT, bus->ss_hcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

449

write32(bus->registers + PCH_IC_SS_SCL_LCNT, bus->ss_lcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

450

write32(bus->registers + PCH_IC_FS_SCL_HCNT, bus->fs_hcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

451

write32(bus->registers + PCH_IC_FS_SCL_LCNT, bus->fs_lcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

453

write32(bus->registers + PCH_IC_HS_SCL_HCNT, bus->hs_hcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

455

write32(bus->registers + PCH_IC_HS_SCL_LCNT, bus->hs_lcnt);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

459

write32(bus->registers + PCH_IC_SDA_HOLD, bus->sda_hold_time);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

472

write32(bus->registers + PCH_IC_RX_TL, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

473

write32(bus->registers + PCH_IC_TX_TL, bus->tx_fifo_depth / 2);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

478

write32(bus->registers + PCH_IC_CON, bus->masterConfig);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

480

write32(bus->registers + PCH_IC_INTR_MASK, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

52

write32(bus->registers + PCH_IC_CLR_RX_UNDER, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

54

write32(bus->registers + PCH_IC_CLR_RX_OVER, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

56

write32(bus->registers + PCH_IC_CLR_TX_OVER, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

58

write32(bus->registers + PCH_IC_CLR_RD_REQ, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

60

write32(bus->registers + PCH_IC_CLR_TX_ABRT, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

62

write32(bus->registers + PCH_IC_CLR_RX_DONE, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

64

write32(bus->registers + PCH_IC_CLR_ACTIVITY, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

66

write32(bus->registers + PCH_IC_CLR_STOP_DET, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

68

write32(bus->registers + PCH_IC_CLR_START_DET, 0);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

70

write32(bus->registers + PCH_IC_CLR_GEN_CALL, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

91

write32(info, reg, value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

106

write32(info, GEN11_GFX_MSTR_IRQ, enable ? GEN11_MASTER_IRQ : 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

114

write32(info, PCH_MASTER_INT_CTL_BDW, enable ? PCH_MASTER_INT_CTL_GLOBAL_BDW : 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

132

write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

143

write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

154

write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

164

write32(info, GEN8_DE_PORT_IIR, iir);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

174

write32(info, GEN11_DE_HPD_IIR, iir);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

184

write32(info, SDEIIR, iir);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

187

write32(info, SHOTPLUG_CTL_DDI, ddiHotplug);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

191

write32(info, SHOTPLUG_CTL_TC, tcHotplug);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

278

write32(info, find_reg(info, INTEL_INTERRUPT_IDENTITY), ~0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

281

write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

282

write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

312

write32(info, INTEL_DISPLAY_A_PIPE_STATUS, value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

315

write32(info, INTEL_DISPLAY_B_PIPE_STATUS, value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

333

write32(info, regIdentity, identity | bit);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

487

write32(info, SDEIER, 0xffffffff);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

488

write32(info, SDEIMR, ~SDE_GMBUS_ICP);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

497

write32(info, GEN8_DE_PORT_IER, mask);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

498

write32(info, GEN8_DE_PORT_IMR, ~mask);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

502

write32(info, GEN8_DE_MISC_IER, GEN8_DE_EDP_PSR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

503

write32(info, GEN8_DE_MISC_IMR, ~GEN8_DE_EDP_PSR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

507

write32(info, GEN11_GU_MISC_IER, GEN11_GU_MISC_GSE);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

508

write32(info, GEN11_GU_MISC_IMR, ~GEN11_GU_MISC_GSE);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

512

write32(info, GEN11_DE_HPD_IER,

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

514

write32(info, GEN11_DE_HPD_IMR, 0xffffffff);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

517

write32(info, GEN11_TC_HOTPLUG_CTL, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

518

write32(info, GEN11_TBT_HOTPLUG_CTL, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

522

write32(info, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

524

write32(info, SDEIMR, 0x3f023f07);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

533

write32(info, SHOTPLUG_CTL_DDI, ctl);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

542

write32(info, SHOTPLUG_CTL_TC, ctl);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

943

write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

944

write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

97

write32(info, regIdentity, ~0);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

98

write32(info, regEnabled, value);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

99

write32(info, regMask, ~value);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

104

write32(info, INTEL6_RC_CONTROL, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

106

write32(info, INTEL6_RC1_WAKE_RATE_LIMIT, 1000 << 16);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

107

write32(info, INTEL6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

108

write32(info, INTEL6_RC6pp_WAKE_RATE_LIMIT, 30);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

109

write32(info, INTEL6_RC_EVALUATION_INTERVAL, 125000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

110

write32(info, INTEL6_RC_IDLE_HYSTERSIS, 25);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

114

write32(info, INTEL6_RC_SLEEP, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

115

write32(info, INTEL6_RC1e_THRESHOLD, 1000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

116

write32(info, INTEL6_RC6_THRESHOLD, 50000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

117

write32(info, INTEL6_RC6p_THRESHOLD, 100000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

118

write32(info, INTEL6_RC6pp_THRESHOLD, 64000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

127

write32(info, INTEL6_RC_CONTROL, rc6Mask | INTEL6_RC_CTL_EI_MODE(1)

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

129

write32(info, INTEL6_RPNSWREQ, INTEL6_FREQUENCY(10) | INTEL6_OFFSET(0)

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

131

write32(info, INTEL6_RC_VIDEO_FREQ, INTEL6_FREQUENCY(12));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

133

write32(info, INTEL6_RP_DOWN_TIMEOUT, 1000000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

134

write32(info, INTEL6_RP_INTERRUPT_LIMITS, maxDelay << 24 | minDelay << 16);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

136

write32(info, INTEL6_RP_UP_THRESHOLD, 59400);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

137

write32(info, INTEL6_RP_DOWN_THRESHOLD, 245000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

138

write32(info, INTEL6_RP_UP_EI, 66000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

139

write32(info, INTEL6_RP_DOWN_EI, 350000);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

141

write32(info, INTEL6_RP_IDLE_HYSTERSIS, 10);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

142

write32(info, INTEL6_RP_CONTROL, INTEL6_RP_MEDIA_TURBO

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

149

write32(info, INTEL6_PCODE_DATA, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

150

write32(info, INTEL6_PCODE_MAILBOX, INTEL6_PCODE_READY

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

165

write32(info, INTEL6_RP_INTERRUPT_LIMITS, limits);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

167

write32(info, INTEL6_RPNSWREQ, INTEL6_FREQUENCY(gtPerfShift)

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

171

write32(info, INTEL6_PMIER, INTEL6_PM_DEFERRED_EVENTS);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

173

write32(info, INTEL6_PMIMR, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

175

write32(info, INTEL6_PMINTRMSK, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

33

write32(info, 0x6204, (1L << 29));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

36

write32(info, 0x42020, (1L << 28) | (1L << 7) | (1L << 5));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

39

write32(info, 0x42020, (1L << 28));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

42

write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

45

write32(info, 0x42020, (1L << 7) | (1L << 5));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

48

write32(info, 0x6204, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

49

write32(info, 0x6208, (1L << 9) | (1L << 7) | (1L << 6));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

50

write32(info, 0x6210, 0);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

57

write32(info, 0x6200, gateValue);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

60

write32(info, 0x6204, (1L << 29) | (1L << 23));

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

62

write32(info, 0x7408, 0x10);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

97

write32(info, INTEL6_RC_STATE, 0);

src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp

89

write32(info.registers + reg, value);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

338

write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

340

write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

343

write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

346

write32(info.registers + AVIVO_VGA_RENDER_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

349

write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

384

write32(info.registers + R600_BUS_CNTL, bus_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

385

write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

386

write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

387

write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

388

write32(info.registers + R600_ROM_CNTL, rom_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

407

write32(info.registers + RADEON_VIPH_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

410

write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

412

write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

415

write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

418

write32(info.registers + AVIVO_VGA_RENDER_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

421

write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

456

write32(info.registers + RADEON_VIPH_CONTROL, viph_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

457

write32(info.registers + R600_BUS_CNTL, bus_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

458

write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

459

write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

460

write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

461

write32(info.registers + R600_ROM_CNTL, rom_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

491

write32(info.registers + RADEON_VIPH_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

494

write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

496

write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

499

write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

502

write32(info.registers + AVIVO_VGA_RENDER_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

505

write32(info.registers + R600_ROM_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

509

write32(info.registers + R600_GENERAL_PWRMGT,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

511

write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

513

write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

515

write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

517

write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

519

write32(info.registers + R600_LOWER_GPIO_ENABLE,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

555

write32(info.registers + RADEON_VIPH_CONTROL, viph_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

556

write32(info.registers + R600_BUS_CNTL, bus_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

557

write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

558

write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

559

write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

560

write32(info.registers + R600_ROM_CNTL, rom_cntl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

561

write32(info.registers + R600_GENERAL_PWRMGT, general_pwrmgt);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

562

write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

564

write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

566

write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

568

write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

570

write32(info.registers + R600_LOWER_GPIO_ENABLE, lower_gpio_enable);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

591

write32(info.registers + RADEON_SEPROM_CNTL1,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

594

write32(info.registers + RADEON_GPIOPAD_A, 0);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

595

write32(info.registers + RADEON_GPIOPAD_EN, 0);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

596

write32(info.registers + RADEON_GPIOPAD_MASK, 0);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

599

write32(info.registers + RADEON_VIPH_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

603

write32(info.registers + RV370_BUS_CNTL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

607

write32(info.registers + AVIVO_D1VGA_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

610

write32(info.registers + AVIVO_D2VGA_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

613

write32(info.registers + AVIVO_VGA_RENDER_CONTROL,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

635

write32(info.registers + RADEON_SEPROM_CNTL1, sepromControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

636

write32(info.registers + RADEON_VIPH_CONTROL, viphControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

637

write32(info.registers + RV370_BUS_CNTL, busControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

638

write32(info.registers + AVIVO_D1VGA_CONTROL, d1vgaControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

639

write32(info.registers + AVIVO_D2VGA_CONTROL, d2vgaControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

640

write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vgaRenderControl);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

641

write32(info.registers + RADEON_GPIOPAD_A, gpioPadA);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

642

write32(info.registers + RADEON_GPIOPAD_EN, gpioPadEN);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

643

write32(info.registers + RADEON_GPIOPAD_MASK, gpioPadMask);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

741

write32(info.registers + RADEON_CONFIG_MEMSIZE,

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

749

write32(info.registers + RADEON_CONFIG_MEMSIZE,

src/add-ons/kernel/drivers/network/ether/wb840/device.c

112

write32(data->reg_base + WB_RXSTART, 0xFFFFFFFF);

src/add-ons/kernel/drivers/network/ether/wb840/device.c

228

write32(device->reg_base + WB_TXSTART, 0xFFFFFFFF);

src/add-ons/kernel/drivers/network/ether/wb840/device.c

265

write32(device->reg_base + WB_TXSTART, 0xFFFFFFFF);

src/add-ons/kernel/drivers/network/ether/wb840/device.c

347

write32(device->reg_base + WB_TXADDR, 0x00000000);

src/add-ons/kernel/drivers/network/ether/wb840/device.c

348

write32(device->reg_base + WB_RXADDR, 0x00000000);

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

108

write32(device->reg_base + WB_SIO, 0);

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

329

write32(device->reg_base + WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

334

write32(device->reg_base + WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

345

write32(device->reg_base + WB_SIO, 0);

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

46

write32(device->reg_base + WB_SIO, \

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

50

write32(device->reg_base + WB_SIO, \

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

190

write32(device->reg_base + WB_BUSCTL,

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

194

write32(device->reg_base + WB_BUSCTL_SKIPLEN, WB_SKIPLEN_4LONG);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

212

write32(device->reg_base + WB_NETCFG, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

213

write32(device->reg_base + WB_BUSCTL, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

214

write32(device->reg_base + WB_TXADDR, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

215

write32(device->reg_base + WB_RXADDR, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

330

write32(device->reg_base + WB_RXSTART, 0xFFFFFFFF);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

404

write32(device->reg_base + WB_ISR, status);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

585

write32(device->reg_base + WB_RXADDR,

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

587

write32(device->reg_base + WB_TXADDR,

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

657

write32(cfgAddress, configFlags);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

80

write32(device->reg_base + WB_IMR, WB_INTRS);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

81

write32(device->reg_base + WB_ISR, 0xFFFFFFFF);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

88

write32(device->reg_base + WB_IMR, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

89

write32(device->reg_base + WB_ISR, 0L);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.h

486

#define WB_SETBIT(reg, x) write32(reg, read32(reg) | x)

src/add-ons/kernel/drivers/network/ether/wb840/wb840.h

487

#define WB_CLRBIT(reg, x) write32(reg, read32(reg) & ~x)

src/system/boot/loader/file_systems/fat/Volume.cpp

388

write32(buffer, 0x1e8, freeClusters - 1);

src/system/boot/loader/file_systems/fat/Volume.cpp

391

write32(buffer, 0x1ec, cluster);