set_opcode
set_opcode(RISC_RESYNC | 0);
set_opcode(RISC_WRITE | RISC_SOL | RISC_EOL | BYTES_PER_LINE);
set_opcode((unsigned long)device->dma_buf1_phys + i * BYTES_PER_LINE);
set_opcode(RISC_SKIP | RISC_IRQ1 | RISC_SOL | 0);
set_opcode(RISC_WRITE | RISC_SOL | RISC_EOL | BYTES_PER_LINE);
set_opcode((unsigned long)device->dma_buf2_phys + i * BYTES_PER_LINE);
set_opcode(RISC_SKIP | RISC_IRQ2 | RISC_SOL | 0);
set_opcode(RISC_JUMP | RISC_SRP);
set_opcode(SRAM_START_ADDRESS + SRAM_BASE_RISC_PROG + 4);