rdmsr
struct nvmm_x86_exit_rdmsr rdmsr;
if (exit->u.rdmsr.msr == MSR_EFER) {
if (exit->u.rdmsr.msr == MSR_NB_CFG) {
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip;
cpudata->hstate.fsbase = rdmsr(MSR_FSBASE);
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_EFER);
svm_global_hstate.star = rdmsr(MSR_STAR);
svm_global_hstate.lstar = rdmsr(MSR_LSTAR);
svm_global_hstate.cstar = rdmsr(MSR_CSTAR);
svm_global_hstate.sfmask = rdmsr(MSR_SFMASK);
if (exit->u.rdmsr.msr == MSR_CR_PAT) {
if (exit->u.rdmsr.msr == MSR_MISC_ENABLE) {
if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = rip + inslen;
vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
vmx_vmwrite(VMCS_HOST_GS_BASE, rdmsr(MSR_GSBASE));
vmx_vmwrite(VMCS_HOST_IA32_PAT, rdmsr(MSR_CR_PAT));
vmx_vmwrite(VMCS_HOST_IA32_EFER, rdmsr(MSR_EFER));
cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_VMX_BASIC);
vmx_cr0_fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0) & ~(CR0_PG|CR0_PE);
vmx_cr0_fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1) | (CR0_PG|CR0_PE);
vmx_cr4_fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);
vmx_cr4_fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
vmx_global_hstate.star = rdmsr(MSR_STAR);
vmx_global_hstate.lstar = rdmsr(MSR_LSTAR);
vmx_global_hstate.cstar = rdmsr(MSR_CSTAR);
vmx_global_hstate.sfmask = rdmsr(MSR_SFMASK);
msr = rdmsr(MSR_IA32_VMX_BASIC);
uint64_t rdmsr(u_int msr);
uint64_t rdmsr(u_int msr);
struct nvmm_x86_exit_rdmsr rdmsr;
if (exit->u.rdmsr.msr == MSR_EFER) {
if (exit->u.rdmsr.msr == MSR_NB_CFG) {
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip;
cpudata->hstate.fsbase = rdmsr(MSR_FSBASE);
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_EFER);
svm_global_hstate.star = rdmsr(MSR_STAR);
svm_global_hstate.lstar = rdmsr(MSR_LSTAR);
svm_global_hstate.cstar = rdmsr(MSR_CSTAR);
svm_global_hstate.sfmask = rdmsr(MSR_SFMASK);
if (exit->u.rdmsr.msr == MSR_CR_PAT) {
if (exit->u.rdmsr.msr == MSR_MISC_ENABLE) {
if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = rip + inslen;
vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
vmx_vmwrite(VMCS_HOST_GS_BASE, rdmsr(MSR_GSBASE));
vmx_vmwrite(VMCS_HOST_IA32_PAT, rdmsr(MSR_CR_PAT));
vmx_vmwrite(VMCS_HOST_IA32_EFER, rdmsr(MSR_EFER));
cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_VMX_BASIC);
vmx_cr0_fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0) & ~(CR0_PG|CR0_PE);
vmx_cr0_fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1) | (CR0_PG|CR0_PE);
vmx_cr4_fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);
vmx_cr4_fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
vmx_global_hstate.star = rdmsr(MSR_STAR);
vmx_global_hstate.lstar = rdmsr(MSR_LSTAR);
vmx_global_hstate.cstar = rdmsr(MSR_CSTAR);
vmx_global_hstate.sfmask = rdmsr(MSR_SFMASK);
msr = rdmsr(MSR_IA32_VMX_BASIC);