rtwn_write_4
rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg);
rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
RTWN_CHK(rtwn_write_4(sc, R92C_RQPN,
rtwn_write_4(sc, wme2reg[ac],
error = rtwn_write_4(sc, R92C_BSSID(id), le32dec(&bssid[0]));
error = rtwn_write_4(sc, R92C_MACID(id), le32dec(&addr[0]));
rtwn_write_4(sc, R92C_BAR_MODE_CTRL, 0x0201ffff);
rtwn_write_4(sc, sc->sc_reg_addr, val);
rtwn_write_4(sc, R92C_CAMCMD,
error = rtwn_write_4(sc, R92C_CAMWRITE, data);
error = rtwn_write_4(sc, R92C_CAMCMD,
error = rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
rtwn_write_4(sc, R92C_MCUFWDL, reg);
rtwn_write_4(sc, R92C_MAR + 0, mfilt[0]);
rtwn_write_4(sc, R92C_MAR + 4, mfilt[1]);
rtwn_write_4(sc, R92C_RCR, sc->rcr);
#define rtwn_bb_write rtwn_write_4
return (rtwn_write_4(sc, addr,
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_MCUTST_1, 0);
rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
rtwn_write_4(sc, R88E_HIMR, 0x00000000);
rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
rtwn_write_4(sc, R88E_HIMR, R88E_INT_ENABLE);
rtwn_write_4(sc, R88E_HIMRE, R88E_INT_ENABLE_EX);
rtwn_write_4(sc, R88E_HISR, 0xffffffff);
rtwn_write_4(sc, R88E_HISRE, 0xffffffff);
rtwn_write_4(sc, R88E_HIMR, R88E_INT_ENABLE);
rtwn_write_4(sc, R88E_HIMRE, R88E_INT_ENABLE_EX);
rtwn_write_4(sc, R88E_HIMR, 0);
rtwn_write_4(sc, R88E_HIMRE, 0);
rtwn_write_4(sc, R88E_HISR, status);
rtwn_write_4(sc, R88E_HISRE, status_ex);
rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
error = rtwn_write_4(sc, R88E_HMEBOX_EXT(sc->fwcur),
error = rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *(uint32_t *)&cmd);
rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
rtwn_write_4(sc, R88E_HISR, 0xffffffff);
rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
rtwn_write_4(sc, R92C_HISR, 0);
rtwn_write_4(sc, R92C_HIMR, 0);
rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
rtwn_write_4(sc, R92C_HISR, 0x00000000);
rtwn_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
rtwn_write_4(sc, R92C_HIMR, R92C_INT_ENABLE);
rtwn_write_4(sc, R92C_HISR, 0xffffffff);
rtwn_write_4(sc, R92C_HIMR, R92C_INT_ENABLE);
rtwn_write_4(sc, R92C_HIMR, 0);
rtwn_write_4(sc, R92C_HISR, status);
rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
error = rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur),
rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
error = rtwn_write_4(sc, R92C_LLT_INIT,
rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
rtwn_write_4(sc, R92C_HISR, 0xffffffff);
rtwn_write_4(sc, R92C_HIMR, 0xffffffff);
rtwn_write_4(sc, R92C_TDECTRL, reg);
rtwn_write_4(sc, R92C_RXDMA_AGG_PG_TH,
rtwn_write_4(sc, R88E_HIMR, 0);
rtwn_write_4(sc, R88E_HIMRE, 0);
rtwn_write_4(sc, R12A_ARFR_5G(0), 0x00000010);
rtwn_write_4(sc, R12A_ARFR_5G(0) + 4, 0xfffff000);
rtwn_write_4(sc, R12A_ARFR_5G(1), 0x00000010);
rtwn_write_4(sc, R12A_ARFR_5G(1) + 4, 0x003ff000);
rtwn_write_4(sc, R12A_ARFR_2G(0), 0x00000015);
rtwn_write_4(sc, R12A_ARFR_2G(0) + 4, 0x003ff000);
rtwn_write_4(sc, R12A_ARFR_2G(1), 0x00000015);
rtwn_write_4(sc, R12A_ARFR_2G(1) + 4, 0xffcff000);
rtwn_write_4(sc, R12A_AMPDU_MAX_LENGTH,
rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03087777);