rtwn_write_2
rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
rtwn_write_2(sc, R92C_RXFLTMAP1, 0);
rtwn_write_2(sc, R92C_BCN_PSR_RPT,
rtwn_write_2(sc, R92C_BCN_INTERVAL(uvp->id), ni->ni_intval);
rtwn_write_2(sc, R92C_RXFLTMAP1,
rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
RTWN_CHK(rtwn_write_2(sc, R92C_TRXFF_BNDY + 2,
error = rtwn_write_2(sc, R92C_BSSID(id) + 4, le16dec(&bssid[4]));
error = rtwn_write_2(sc, R92C_MACID(id) + 4, le16dec(&addr[4]));
rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
rtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
rtwn_write_2(sc, R92C_RL,
rtwn_write_2(sc, R92C_SECCFG, seccfg);
error = rtwn_write_2(sc, R92C_SYS_FUNC_EN,
error = rtwn_write_2(sc, R92C_SYS_CLKR,
rtwn_write_2(sc, R92C_RXFLTMAP0, filter);
rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
rtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000);
return (rtwn_write_2(sc, addr,
rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid));
rtwn_write_2(sc, R92C_CR, 0);
rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
rtwn_write_2(sc, R92C_SYS_FUNC_EN,
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
rtwn_write_2(sc, R88E_TX_RPT_TIME, 0xcdf0);
rtwn_write_2(sc, R92C_APS_FSMCO,
rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL,
rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
error = rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur),
rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
rtwn_write_2(sc, R92C_SYS_CLKR,
rtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
rtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
rtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
rtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
rtwn_write_2(sc, R92C_SYS_CLKR,
rtwn_write_2(sc, R92C_APS_FSMCO,
rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
rtwn_write_2(sc, R92C_RXDMA_STATUS, 0x7400);
rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x1f1f);
rtwn_write_2(sc, R92C_RXDMA_AGG_PG_TH,
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));