rtwn_setbits_2
RTWN_CHK(rtwn_setbits_2(sc, R92C_TRXDMA_CTRL,
rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, 0xff00,
rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC);
rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, R92C_SYS_ISO_CTRL_DIOR, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_CR,
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0x100);
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, 0x014, 0, 0x0180);
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,