rtwn_setbits_1_shift
rtwn_setbits_1_shift(sc, R92C_CR, 0, R92C_CR_ENSWBCN, 1);
rtwn_setbits_1_shift(sc, R92C_FWHW_TXQ_CTRL,
rtwn_setbits_1_shift(sc, R92C_FWHW_TXQ_CTRL,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSWBCN, 0, 1);
rtwn_setbits_1_shift(sc, sc->bcn_status_reg[id],
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_MCUFWDL, R92C_MCUFWDL_ROM_DLEN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 0,
rtwn_setbits_1_shift(sc, R92C_MCUFWDL, R92C_MCUFWDL_ROM_DLEN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_ISO_CTRL,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_MCUFWDL, R92C_MCUFWDL_ROM_DLEN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL,
rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
RTWN_CHK(rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_TXDMA_OFFSET_CHK, 0,