rtwn_setbits_1
rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id),
rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id),
rtwn_setbits_1(sc, R92C_MSR, R92C_MSR_MASK << id * 2, mode << id * 2);
rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id),
rtwn_setbits_1(sc, R92C_TXPAUSE, 0, R92C_TX_QUEUE_AC);
rtwn_setbits_1(sc, R92C_TXPAUSE, 0,
rtwn_setbits_1(sc, R92C_TXPAUSE, 0, R92C_TX_QUEUE_BCN);
rtwn_setbits_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_BCN, 0);
rtwn_setbits_1(sc, R92C_ACMHWCTRL, R92C_ACMHWCTRL_ACM_MASK, acm);
rtwn_setbits_1(sc, R92C_FWHW_TXQ_CTRL, 0,
rtwn_setbits_1(sc, R92C_CR, 0, R92C_CR_MACTXEN | R92C_CR_MACRXEN);
rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENBT, 0);
rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id),
rtwn_setbits_1(sc, R92C_MCUFWDL, 0, R92C_MCUFWDL_CHKSUM_RPT);
return (rtwn_setbits_1(sc, addr + shift, clr >> shift * NBBY,
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
rtwn_setbits_1(sc, R92C_MBID_NUM, 0, R88E_MBID_TXBCN_RPT(id));
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_MBID_NUM, R88E_MBID_TXBCN_RPT(id), 0);
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ);
rtwn_setbits_1(sc, R92C_MCUFWDL, 0, R92C_MCUFWDL_EN);
rtwn_setbits_1(sc, R92C_MCUFWDL, R92C_MCUFWDL_EN, 0);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0x6f,
rtwn_setbits_1(sc, R92C_MAC_PINMUX_CFG, 0x01, 0);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0x0f, 0x60);
RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0,
RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0x02, 0);
rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_RFKILL, 0);
rtwn_setbits_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF, 0);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_BB_GLB_RST);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0x0f,
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_BCN_CTRL(id),
rtwn_setbits_1(sc, R92C_BWOPMODE, R92C_BWOPMODE_20MHZ, 0);
rtwn_setbits_1(sc, R92C_RRSR + 2, 0x6f, (prichlo ? 1 : 2) << 5);
rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ);
rtwn_setbits_1(sc, R92C_MCUFWDL, 0, R92C_MCUFWDL_EN);
rtwn_setbits_1(sc, R92C_MCUFWDL, R92C_MCUFWDL_EN, 0);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0, 0x80);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);
rtwn_setbits_1(sc, 0x16, 0xf0, 0x90);
RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
RTWN_CHK(rtwn_setbits_1(sc, R92C_APSD_CTRL,
rtwn_setbits_1(sc, R92C_LDOV12D_CTRL,
rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0);
rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);
rtwn_setbits_1(sc, 0xcc, 0, 0x4);
rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0);
rtwn_setbits_1(sc, R92C_LEDCFG1, 0, R92C_LEDCFG1_DIS);
rtwn_setbits_1(sc, R92C_LEDCFG1, R92C_LEDCFG1_DIS, 0);
rtwn_setbits_1(sc, R12A_RXDMA_PRO, 0x20, 0x1e);
rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
rtwn_setbits_1(sc, R92C_QUEUE_CTRL, 0x08, 0);
rtwn_setbits_1(sc, R92C_BCN_CTRL(0), R92C_BCN_CTRL_EN_BCN, 0);
rtwn_setbits_1(sc, R92C_BCN_CTRL(1), R92C_BCN_CTRL_EN_BCN, 0);
rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);
rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);
rtwn_setbits_1(sc, R92C_RSV_CTRL, R92C_RSV_CTRL_WLOCK_00, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x08, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL, R92C_RSV_CTRL_WLOCK_00, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x08);
rtwn_setbits_1(sc, R92C_MCUFWDL, 0, R92C_MCUFWDL_EN);
rtwn_setbits_1(sc, R92C_MCUFWDL, R92C_MCUFWDL_EN, 0);
return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M,
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0,
RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0);
rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0);
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0);
rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0);
rtwn_setbits_1(sc, R92C_LEDCFG0, 0x8f,
rtwn_setbits_1(sc, R92C_FWHW_TXQ_CTRL,
rtwn_setbits_1(sc, R12A_HT_SINGLE_AMPDU, 0,
rtwn_setbits_1(sc, R92C_RSV_CTRL, 0, 0x60);
rtwn_setbits_1(sc, R92C_QUEUE_CTRL, 0x08, 0);
rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M,
rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M,
rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M,
rtwn_setbits_1(sc, 0xf008, 0x18, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL, 0x02, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL, 0x02, 0);
rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
RTWN_CHK(rtwn_setbits_1(sc, R92C_LEDCFG3, 0, 0x01));
RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0, 0x30));
RTWN_CHK(rtwn_setbits_1(sc, 0x025, 0x40, 0));
RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0, 0x02));
RTWN_CHK(rtwn_setbits_1(sc, 0x063, 0, 0x02));
RTWN_CHK(rtwn_setbits_1(sc, 0x062, 0x02, 0));
RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR, 0, 0x01));
RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR + 2, 0, 0x02));
RTWN_CHK(rtwn_setbits_1(sc, R92C_APE_PLL_CTRL_EXT + 2, 0xFF, 0x82));
RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_MISC, 0, 0x40));
RTWN_CHK(rtwn_setbits_1(sc, R92C_LDO_SWR_CTRL, 0, 0x40));
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
rtwn_setbits_1(sc, R92C_LEDCFG3, 0x01, 0);
rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0x02, 0);
rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL, 0, R92C_SYS_ISO_CTRL_IP2MAC);
rtwn_setbits_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_EN, 0);
rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0, 0x01);
RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0x01, 0));
RTWN_CHK(rtwn_setbits_1(sc, R92C_LDOA15_CTRL, 0, R92C_LDOA15_CTRL_EN));
RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0x10, 0));
RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,