rtwn_read_4
reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL);
val = rtwn_read_4(sc, sc->sc_reg_addr);
reg = rtwn_read_4(sc, R92C_SYS_CFG);
if (rtwn_read_4(sc, reg) & R92C_TDECTRL_BCN_VALID) {
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
reg = rtwn_read_4(sc, R92C_MCUFWDL);
if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
return (rtwn_read_4(sc, R92C_TSFTR(id)));
return (rtwn_read_4(sc, R92C_TSFTR(id) + 4));
#define rtwn_bb_read rtwn_read_4
(rtwn_read_4(sc, addr) & ~clr) | set));
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
status = rtwn_read_4(sc, R88E_HISR);
status_ex = rtwn_read_4(sc, R88E_HISRE);
vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
status = rtwn_read_4(sc, R92C_HISR);
if (MS(rtwn_read_4(sc, R92C_HPON_FSM),
vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
reg = rtwn_read_4(sc, R92C_TDECTRL);
if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT))
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
!!(rtwn_read_4(sc, R92C_MULTI_FUNC_CTRL) & R92C_MULTI_BT_FUNC_EN);