rtwn_read_1
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
(rtwn_read_1(sc, addr) & ~clr) | set));
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
status = rtwn_read_1(sc, R92C_C2H_EVT_CLEAR);
len = rtwn_read_1(sc, R92C_C2H_EVT_MSG);
if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);
if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
txmode = rtwn_read_1(sc, R12A_SINGLETONE_CONT_TX + 2);
!(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ))
if (rtwn_read_1(sc, 0x837) & 0x04)
if (rtwn_read_1(sc, 0x837) & 0x04)
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
if ((rtwn_read_1(sc, R92C_USB_INFO) & 0x30) == 0) {
if (rtwn_read_1(sc, R92C_TYPE_ID + 3) & 0x80)
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)