rtwn_bb_write
rtwn_bb_write(sc, R92C_TX_IQK, 0x80007c00 | (tx[0] << 16) | tx[1]);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x30008c1c);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1c);
rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160c05);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160c05);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x0f600000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x30008c1c);
rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160804);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160000);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0);
rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
rtwn_bb_write(sc, reg_adda[i], 0x04db25a4);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
rtwn_bb_write(sc, 0x0b68, 0x00080000);
rtwn_bb_write(sc, 0x0b6c, 0x00080000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
rtwn_bb_write(sc, 0x0b68, 0x00080000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4);
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA,
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1),
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f);
rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22);
rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102);
rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0);
rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
rtwn_bb_write(sc, reg_adda[i], 0x04db25a4);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000);
rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4);
rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f);
rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202);
rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22);
rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22);
rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102);
rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202);
rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL,
rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);
rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
rtwn_bb_write(sc, regs[i], vals[i]);
rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0);
rtwn_bb_write(sc, R12A_PMPD(0), 0);
rtwn_bb_write(sc, 0xc88, 0);
rtwn_bb_write(sc, 0xc8c, 0x3c000000);
rtwn_bb_write(sc, R12A_SLEEP_NAV(1), 0);
rtwn_bb_write(sc, R12A_PMPD(1), 0);
rtwn_bb_write(sc, 0xe88, 0);
rtwn_bb_write(sc, 0xe8c, 0x3c000000);
rtwn_bb_write(sc, R12A_RFE(0), rfe[0]);
rtwn_bb_write(sc, R12A_RFE(1), rfe[1]);
rtwn_bb_write(sc, R12A_TXAGC_NSS1IX3_1IX0(chain),
rtwn_bb_write(sc, R12A_TXAGC_NSS1IX7_1IX4(chain),
rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain),
rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain),
rtwn_bb_write(sc, R12A_TXAGC_NSS2IX5_2IX2(chain),
rtwn_bb_write(sc, R12A_TXAGC_NSS2IX9_2IX6(chain),
rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain),
rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain),
rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain),
rtwn_bb_write(sc, R12A_RFMOD, val);
rtwn_bb_write(sc, R12A_CCA_ON_SEC, val);
rtwn_bb_write(sc, R12A_RFMOD, val);
rtwn_bb_write(sc, R12A_CCA_ON_SEC, val);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain),
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain),
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain),
rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain),
rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
rtwn_bb_write(sc, 0x81c, agc_prog->val[j]);
rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22);
rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20);
rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
rtwn_bb_write(sc, R12A_LSSI_PARAM(chain),
rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0);
rtwn_bb_write(sc, R12A_PMPD(0), 0);
rtwn_bb_write(sc, 0xc88, 0);
rtwn_bb_write(sc, 0xc8c, 0x3c000000);
rtwn_bb_write(sc, 0xc90, 0x80);
rtwn_bb_write(sc, 0xc94, 0);
rtwn_bb_write(sc, 0xcc4, 0x20040000);
rtwn_bb_write(sc, 0xcc8, 0x20000000);
rtwn_bb_write(sc, 0xcb8, 0);
rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
RTWN_CHK(rtwn_bb_write(sc, 0x924, 0x0152a400));
RTWN_CHK(rtwn_bb_write(sc, 0x91c, 0x0fa21a20));
RTWN_CHK(rtwn_bb_write(sc, 0x920, 0xe0f57204));
RTWN_CHK(rtwn_bb_write(sc, 0x918, 0x1c16ecdf));