rtwn_bb_setbits
rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x3ff, reg);
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(0), 0xf0000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x003f0000,
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0x3ff,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0xfc00,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0),
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000,
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000,
rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000,
rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00,
rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000,
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10,
rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00,
rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE,
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0,
rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0),
rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(1),
rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02);
rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022);
rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000,
rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23);
rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10);
rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000);
rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000);
rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000);
rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000);
rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(idx),
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);
rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM,
rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10);
rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), R92C_HSSI_PARAM2_READ_EDGE, 0);
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), 0, R92C_HSSI_PARAM2_READ_EDGE);
rtwn_bb_setbits(sc, 0x818, 0x20000, 0);
rtwn_bb_setbits(sc, 0x818, 0, 0x20000);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);
rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x03, 0x0c);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000);
rtwn_bb_setbits(sc, 0xc90, 0, 0x00000080);
rtwn_bb_setbits(sc, 0xcc4, 0, 0x20040000);
rtwn_bb_setbits(sc, 0xcc8, 0, 0x20000000);
rtwn_bb_setbits(sc, 0xe90, 0, 0x00000080);
rtwn_bb_setbits(sc, 0xec4, 0, 0x20040000);
rtwn_bb_setbits(sc, 0xec8, 0, 0x20000000);
rtwn_bb_setbits(sc, R12A_TX_PWR_TRAINING(chain),
rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);
rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M,
rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);
rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300202);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);
rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN,
rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);
rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK,
rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);
rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);
rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0, 0x08);
rtwn_bb_setbits(sc, R12A_HSSI_PARAM2,
rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x08, 0);
rtwn_bb_setbits(sc, R12A_HSSI_PARAM2,
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000);
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK,
rtwn_bb_setbits(sc, R12A_TX_SCALE(0), 0x0f00, 0x0100);
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0);
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07);
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700);
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN,
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000);
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0);
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0x05, 0x02);
rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0x0500, 0x0200);
rtwn_bb_setbits(sc, R12A_TX_SCALE(0), 0x0f00, 0);
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
rtwn_bb_setbits(sc, 0x924, 0x00008000, 0);
error = rtwn_bb_setbits(sc, 0x924, 0x00008000, 0);
return (rtwn_bb_setbits(sc, 0x924, 0, 0x00008000));
RTWN_CHK(rtwn_bb_setbits(sc, 0x814, 0x3fffffff, 0x04cc4d10));
RTWN_CHK(rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0xff, 0x06));