rtwn_bb_read
tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(0)),
tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)),
status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(0)),
vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(0));
status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
reg = rtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)),
tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)),
rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)),
rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)),
vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)),
tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)),
rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)),
rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)),
vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);
val = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
vals[i] = rtwn_bb_read(sc, regs[i]);
rfe[0] = rtwn_bb_read(sc, R12A_RFE(0));
rfe[1] = rtwn_bb_read(sc, R12A_RFE(1));
val = rtwn_bb_read(sc, R12A_RFMOD);
val = rtwn_bb_read(sc, R12A_CCA_ON_SEC);
val = rtwn_bb_read(sc, R12A_RFMOD);
val = rtwn_bb_read(sc, R12A_CCA_ON_SEC);
if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR)
reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
val = rtwn_bb_read(sc, R12A_HSSI_PARAM1(chain));
val = rtwn_bb_read(sc, pi_mode ? R12A_HSPI_READBACK(chain) :
val = rtwn_bb_read(sc, R12A_HSSI_PARAM1(chain));
val = rtwn_bb_read(sc, pi_mode ? R12A_HSPI_READBACK(chain) :
reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
return !!(rtwn_bb_read(sc, 0xf98) & 0x00020000);
return !!(rtwn_bb_read(sc, 0x924) & 0x00008000);