r4
ulong r4;
#define _rule_(r1, r2, r3, r4) (((r1) << 12) | ((r2) << 8) | ((r3) << 4) | (r4))
ulong r4;
r3,r4,r5,r6,r7,r8,r9,r10, /* volatile regs */
uint32 r4;
uint32 r4;
uint32 r4;
int32_t r1, r2, r3, r4, temp;
r4 = le32toh(sc->rawtemp);
r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
temp = (259 * (r4 - r2)) / (r3 - r1);
uint32_t r1, r2, r4;
rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4);
uint32_t r1, r2, r3, r4;
rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
uint32_t r1, r2, r3, r4;
uint32_t r2, r3, r4;
r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
rt2860_rf_write(sc, RT2860_RF4, r4);
rt2860_rf_write(sc, RT2860_RF4, r4);
rt2860_rf_write(sc, RT2860_RF4, r4);
cmd.r4 = 0;
uint32_t r4;
rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
uint32_t r1, r2, r3, r4;
uint32_t r2, r3, r4;
r4 = (rfprog[i].r4 & ~(0x001f87c0)) | (sc->freq << 15);
r4 |= (txpow2 << 7) | (1 << 6);
r4 |= (txpow2 << 7);
r4 |= (txpow2 << 6);
run_rt2870_rf_write(sc, r4);
run_rt2870_rf_write(sc, r4);
run_rt2870_rf_write(sc, r4);
uint32_t r1, r2, r3, r4;
ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4);
uint32_t r4;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
r4 = (q4 >> 8) | (q4 << 24);
q[4] = q3 ^ r3 ^ q7 ^ r7 ^ r4 ^ rotr16(q4 ^ r4);
q[5] = q4 ^ r4 ^ r5 ^ rotr16(q5 ^ r5);
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
r4 = (q4 >> 8) | (q4 << 24);
q[4] = q1 ^ q2 ^ q3 ^ q5 ^ r1 ^ r3 ^ r4 ^ r5 ^ r6 ^ r7 ^ rotr16(q1 ^ q2 ^ q4 ^ q5 ^ q7 ^ r1 ^ r4 ^ r5 ^ r6);
q[5] = q2 ^ q3 ^ q4 ^ q6 ^ r2 ^ r4 ^ r5 ^ r6 ^ r7 ^ rotr16(q2 ^ q3 ^ q5 ^ q6 ^ r2 ^ r5 ^ r6 ^ r7);
q[7] = q4 ^ q5 ^ q6 ^ r4 ^ r6 ^ r7 ^ rotr16(q4 ^ q5 ^ q7 ^ r4 ^ r7);
#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
register t4 _n4 __asm(#r4) = _##name##_v4; \
frame->r4, frame->r5, frame->r6, frame->r7);
frame->r4, frame->r5, frame->r6, frame->r7);
signalFrameData->context.uc_mcontext.r4 = frame->r4;
frame->r4 = signalFrameData->context.uc_mcontext.r4;
frame->r4, frame->r5, frame->r6, frame->r7);
dprintf("r4-r7: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r4, frame->r5, frame->r6, frame->r7);
li r4, 0; \
STORE_RETURN_VALUE (r4); \
STORE_RETURN_BOUNDS (r4, r4)
r4 = 1.86459191715652901344e-02, /* 0x3F9317EA, 0x742ED475 */
q = 1.0+y*(r1+y*(r2+y*(r3+y*(r4+y*(r5+y*r6)))));
q = 1.0f+y*(r1+y*(r2+y*(r3+y*(r4+y*(r5+y*r6)))));
r4 = 1.8645919859e-02, /* 0x3c98bf54 */
r4 = -5.563807682263923279438235987186184968542E5L,
q = r0 + y * (r1 + y * (r2 + y * (r3 + y * (r4 + y * (r5 + y * (r6 + y))))));
r4 = r2 * r2;
p = A[0] + r * A[1] + r2 * (A[2] + r * A[3]) + r4 * (A[4] + r * A[5]);
double_t z, r, r2, r4, y, invc, logc, kd, hi, lo, t1, t2, t3, p;
r4 = r2 * r2;
lo += r4 * (B[2] + r * B[3] + r2 * (B[4] + r * B[5]) +
r4 * (B[6] + r * B[7] + r2 * (B[8] + r * B[9])));
double_t z, r, r2, r4, p, q, y, y0, invc, logc;
r4 = r2 * r2;
y = y * r4 + q;