r3
int r3 = -(r / 3);
while(dy <= r3);
base_type::solid_rectangle(x+r3+1, y+r3+1, x-r3-1, y-r3-1);
ulong r3;
#define _rule_(r1, r2, r3, r4) (((r1) << 12) | ((r2) << 8) | ((r3) << 4) | (r4))
ulong r3;
r3,r4,r5,r6,r7,r8,r9,r10, /* volatile regs */
uint32 r3;
uint32 r3;
uint32 r3;
ath_rate_sample_max_4ms_framelen[idx][MCS_IDX(sched->r3)]);
rc[3].rix = sched->r3;
rix3 = sched->r3;
uint8_t t3, r3; /* series 3: tries, rate code */
int32_t r1, r2, r3, r4, temp;
r3 = le32toh(uc->temp[2].chan20MHz);
if (r1 == r3) /* Prevents division by 0 (should not happen). */
temp = (259 * (r4 - r2)) / (r3 - r1);
uint32_t r1, r2, r3, r4;
rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
uint32_t r1, r2, r3, r4;
uint32_t r2, r3, r4;
r3 = rfprog[i].r3 | txpow1 << 7;
rt2860_rf_write(sc, RT2860_RF3, r3);
rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
rt2860_rf_write(sc, RT2860_RF3, r3);
cmd.r3 = 0;
uint32_t r3;
rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7);
rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7 | 1);
rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7);
uint32_t r1, r2, r3, r4;
uint32_t r2, r3, r4;
r3 = rfprog[i].r3 & 0xffffc1ff;
r3 |= (txpow1 << 10) | (1 << 9);
r3 |= (txpow1 << 10);
r3 |= (txpow1 << 9);
run_rt2870_rf_write(sc, r3 & ~(1 << 2));
run_rt2870_rf_write(sc, r3 | (1 << 2));
run_rt2870_rf_write(sc, r3 & ~(1 << 2));
uint32_t r1, r2, r3, r4;
uint32_t r1, r2, r3;
error = zyd_rfwrite(sc, rfprog[chan - 1].r3);
uint32_t r1, r2, r3;
error = zyd_rfwrite_cr(sc, rfprog[chan - 1].r3);
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
r3 = (q3 >> 8) | (q3 << 24);
q[3] = q2 ^ r2 ^ q7 ^ r7 ^ r3 ^ rotr16(q3 ^ r3);
q[4] = q3 ^ r3 ^ q7 ^ r7 ^ r4 ^ rotr16(q4 ^ r4);
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
r3 = (q3 >> 8) | (q3 << 24);
q[3] = q0 ^ q1 ^ q2 ^ q5 ^ q6 ^ r0 ^ r2 ^ r3 ^ r5 ^ rotr16(q0 ^ q1 ^ q3 ^ q5 ^ q6 ^ q7 ^ r0 ^ r3 ^ r5 ^ r7);
q[4] = q1 ^ q2 ^ q3 ^ q5 ^ r1 ^ r3 ^ r4 ^ r5 ^ r6 ^ r7 ^ rotr16(q1 ^ q2 ^ q4 ^ q5 ^ q7 ^ r1 ^ r4 ^ r5 ^ r6);
q[6] = q3 ^ q4 ^ q5 ^ q7 ^ r3 ^ r5 ^ r6 ^ r7 ^ rotr16(q3 ^ q4 ^ q6 ^ q7 ^ r3 ^ r6 ^ r7);
#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
register t3 _n3 __asm(#r3) = _##name##_v3; \
frame->r0, frame->r1, frame->r2, frame->r3);
frame->r0, frame->r1, frame->r2, frame->r3,
signalFrameData->context.uc_mcontext.r3 = frame->r3;
frame->r3 = signalFrameData->context.uc_mcontext.r3;
frame->r0, frame->r1, frame->r2, frame->r3);
dprintf("r0-r3: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r0, frame->r1, frame->r2, frame->r3);
FPU_SUBCS(r3, x->fp_mant[3], y->fp_mant[3]);
if ((r0 | r1 | r2 | r3) == 0) {
FPU_SUBS(r3, 0, r3);
r->fp_mant[3] = r3;
uint32_t r0, r1, r2, r3;
u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
r3 = x->fp_mant[3];
r0 = d0, r1 = d1, r2 = d2, r3 = d3;
x->fp_sticky = r0 | r1 | r2 | r3;
register uintptr_t r3 __asm__("r3") = __a_cas_ptr;
: "+r"(r0), "+r"(r3) : "r"(r1), "r"(r2)
r3 = 1.71933865632803078993e-01, /* 0x3FC601ED, 0xCCFBDF27 */
q = 1.0+y*(r1+y*(r2+y*(r3+y*(r4+y*(r5+y*r6)))));
q = 1.0f+y*(r1+y*(r2+y*(r3+y*(r4+y*(r5+y*r6)))));
r3 = 1.7193385959e-01, /* 0x3e300f6e */
r3 = -4.310526301881305003489257052083370058799E6L,
q = r0 + y * (r1 + y * (r2 + y * (r3 + y * (r4 + y * (r5 + y * (r6 + y))))));
double_t w, z, r, r2, r3, y, invc, logc, kd, hi, lo;
r3 = r * r2;
y = r3 *
r3 * (B[4] + r * B[5] + r2 * B[6] +
r3 * (B[7] + r * B[8] + r2 * B[9] + r3 * B[10])));
Row* r3 = layout->AddRow(r2->Bottom(), layout->Bottom());
layout->AddView(b3, r3, c1);