r10
ulong r10;
uint64 r10;
ulong r10;
r3,r4,r5,r6,r7,r8,r9,r10, /* volatile regs */
unsigned long r10;
uint32 r10;
uint32 r10;
uint32 r10;
uint64 r10;
movq %r10,TF_R10(%rsp) ; \
movq %rax,%r10 ; \
movq PCPU(trampoline)+TR_CR2, %r10 ; \
movq %cr2, %r10 ; \
movq %r10, TF_ADDR(%rsp) ; \
movq TF_R10(%rsp),%r10 ; \
x64State->r10 = IntRegisterValue(X86_64_REGISTER_R10);
SetIntRegister(X86_64_REGISTER_R10, state.r10);
movq %r10,TF_R10(%rsp) ; \
movq %rax,%r10 ; \
movq PCPU(trampoline)+TR_CR2, %r10 ; \
movq %cr2, %r10 ; \
movq %r10, TF_ADDR(%rsp) ; \
movq TF_R10(%rsp),%r10 ; \
#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t10 _n10 __asm(#r10) = _##name##_v10; \
#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
register t10 _n10 __asm(#r10) = _##name##_v10; \
#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
register t10 _n10 __asm(#r10) = _##name##_v10; \
frame->r8, frame->r9, frame->r10, frame->r11);
frame->r8, frame->r9, frame->r10, frame->r11,
signalFrameData->context.uc_mcontext.r10 = frame->r10;
frame->r10 = signalFrameData->context.uc_mcontext.r10;
frame->r8, frame->r9, frame->r10, frame->r11);
dprintf("r8-r11: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r8, frame->r9, frame->r10, frame->r11);
signalFrameData->context.uc_mcontext.r10 = frame->r10;
frame->r10 = signalFrameData->context.uc_mcontext.r10;
{ B_UINT64_TYPE, frame->r10 }, { B_UINT64_TYPE, frame->r11 },
kprintf(" r10 %#-18lx r11 %#-18lx r12 %#lx\n", frame->r10,
CHECK_DEBUG_VARIABLE("r10", frame->r10, true);
frame->r10 = cpuState->r10;
cpuState->r10 = frame->r10;
DEFINE_OFFSET_MACRO(IFRAME, iframe, r10);