reg_write32
reg_write32(REG_AUD_INT_STAT, 0xffffffff);
reg_write32(REG_TS_INT_STAT, 0xffffffff);
reg_write32(REG_VIP_INT_STAT, 0xffffffff);
reg_write32(REG_HST_INT_STAT, 0xffffffff);
reg_write32(REG_DMA_RISC_INT_MSK, 0xffffffff);
reg_write32(REG_PDMA_STHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
reg_write32(REG_PDMA_DTHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
reg_write32(REG_TS_GP_CNT_CNTRL, 0x3);
reg_write32(REG_TS_LNGTH, BYTES_PER_LINE);
reg_write32(REG_TS_GEN_CONTROL, reg_read32(REG_TS_GEN_CONTROL) | TS_GEN_CONTROL_IPB_SMODE);
reg_write32(REG_HW_SOP_CONTROL, (MPEG2_SYNC_BYTE << 16) | (MPEG2_PACKET_SIZE << 4) | SYNC_PACKET_COUNT);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) | 0x18000);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) & ~0x06000);
reg_write32(REG_PCI_INT_MSK, reg_read32(REG_PCI_INT_MSK) | PCI_INT_STAT_TS_INT | 0x00fc00);
reg_write32(REG_TS_INT_MSK, reg_read32(REG_TS_INT_MSK) | TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2 | 0x1f1100);
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) | DEV_CNTRL2_RUN_RISC);
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) | TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN);
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) & ~(TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN));
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) & ~DEV_CNTRL2_RUN_RISC);
reg_write32(REG_TS_INT_STAT, mstat);
reg_write32(REG_PCI_INT_MSK, 0);
reg_write32(REG_PCI_INT_MSK, 0);
reg_write32(REG_PCI_INT_STAT, wmstat);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CDT, SRAM_START_ADDRESS + SRAM_BASE_FIFO_0);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CDT + 16, SRAM_START_ADDRESS + SRAM_BASE_FIFO_1);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x00, SRAM_START_ADDRESS + SRAM_BASE_RISC_PROG);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x04, SRAM_START_ADDRESS + SRAM_BASE_CDT);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x08, (2 * 16) / 8); // FIFO count = 2
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x0c, SRAM_START_ADDRESS + SRAM_BASE_RISC_QUEUE);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x10, 0x80000000 | (0x100 / 4));
reg_write32(REG_DMA28_PTR1, SRAM_START_ADDRESS + SRAM_BASE_FIFO_0);
reg_write32(REG_DMA28_PTR2, SRAM_START_ADDRESS + SRAM_BASE_CDT);
reg_write32(REG_DMA28_CNT1, BYTES_PER_LINE / 8);
reg_write32(REG_DMA28_CNT2, (2 * 16) / 8); // FIFO count = 2
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 | F2_DEV_CNTRL1_EN_VSFX);
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 & ~F2_DEV_CNTRL1_EN_VSFX);
reg_write32(0x38c06c, 1);
reg_write32(REG_DEV_CNTRL2, 0);
reg_write32(REG_TS_DMA_CNTRL, 0x0);
reg_write32(REG_VIP_STREAM_EN, 0x0);
reg_write32(REG_HST_STREAM_EN, 0x0);
reg_write32(REG_PCI_INT_MSK, 0x0);
reg_write32(REG_VID_INT_MSK, 0x0);
reg_write32(REG_AUD_INT_MSK, 0x0);
reg_write32(REG_TS_INT_MSK, 0x0);
reg_write32(REG_VIP_INT_MSK, 0x0);
reg_write32(REG_HST_INT_MSK, 0x0);
reg_write32(REG_DMA_RISC_INT_MSK, 0x0);
reg_write32(REG_PCI_INT_STAT, 0xffffffff);
reg_write32(REG_VID_INT_STAT, 0xffffffff);
reg_write32(REG_I2C_CONTROL, device->i2c_reg);
reg_write32(REG_I2C_CONTROL, device->i2c_reg);
reg_write32(REG_I2C_CONTROL, device->i2c_reg);