reg_read32
reg_write32(REG_TS_GEN_CONTROL, reg_read32(REG_TS_GEN_CONTROL) | TS_GEN_CONTROL_IPB_SMODE);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) | 0x18000);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) & ~0x06000);
reg_write32(REG_PCI_INT_MSK, reg_read32(REG_PCI_INT_MSK) | PCI_INT_STAT_TS_INT | 0x00fc00);
reg_write32(REG_TS_INT_MSK, reg_read32(REG_TS_INT_MSK) | TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2 | 0x1f1100);
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) | DEV_CNTRL2_RUN_RISC);
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) | TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN);
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) & ~(TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN));
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) & ~DEV_CNTRL2_RUN_RISC);
uint32 mstat = reg_read32(REG_TS_INT_MSTAT);
mstat = reg_read32(REG_PCI_INT_MSTAT);
", mstat 0x%08" B_PRIx32 "\n", reg_read32(REG_PCI_INT_MSK),
reg_read32(REG_PCI_INT_STAT), mstat);
dev_cntrl1 = reg_read32(REG_F2_DEV_CNTRL1);
reg_read32(REG_I2C_CONTROL); // PCI bridge flush
reg_read32(REG_I2C_CONTROL); // PCI bridge flush
return (reg_read32(REG_I2C_CONTROL) & I2C_SCL) >> 1; // I2C_SCL is 0x02
return reg_read32(REG_I2C_CONTROL) & I2C_SDA; // I2C_SDA is 0x01
device->i2c_reg = reg_read32(REG_I2C_CONTROL);
reg_read32(REG_I2C_CONTROL); // PCI bridge flush