src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

108

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

111

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

126

write32(targetRegister, read32(targetRegister) & ~FDI_TX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

127

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

152

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

155

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

165

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

168

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

177

return (read32(FDI_RX_CTL(fPipeIndex)) & FDI_RX_PLL_ENABLED) != 0;

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

186

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

203

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

206

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

216

write32(targetRegister, read32(targetRegister) & ~FDI_RX_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

217

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

227

write32(targetRegister, (read32(targetRegister) & ~FDI_RX_CLOCK_MASK)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

229

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

255

*bitsPerPixel = ((read32(rxControl) & FDI_RX_LINK_BPC_MASK) >> FDI_RX_LINK_COLOR_SHIFT);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

285

*lanes = ((read32(txControl) & FDI_DP_PORT_WIDTH_MASK) >> FDI_DP_PORT_WIDTH_SHIFT) + 1;

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

294

TRACE("%s: FDI TX ctrl before: 0x%" B_PRIx32 "\n", __func__, read32(txControl));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

295

TRACE("%s: FDI RX ctrl before: 0x%" B_PRIx32 "\n", __func__, read32(rxControl));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

301

write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

302

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

303

write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

304

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

306

write32(txControl, (read32(txControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

307

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

309

write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_PATTERN_MASK_CPT) | FDI_LINK_TRAIN_PATTERN_1_CPT);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

311

write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

313

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

359

TRACE("%s: FDI TX ctrl after: 0x%" B_PRIx32 "\n", __func__, read32(txControl));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

360

TRACE("%s: FDI RX ctrl after: 0x%" B_PRIx32 "\n", __func__, read32(rxControl));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

377

uint32 tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

387

tmp = read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

398

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

403

write32(rxControl, read32(rxControl)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

405

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

420

uint32 tmp = read32(FDI_RX_IMR(fPipeIndex));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

427

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

435

tmp = read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

457

tmp = read32(iirControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

473

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

478

tmp = read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

483

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

487

tmp = read32(iirControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

515

uint32 tmp = read32(imrControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

519

read32(imrControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

522

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

535

tmp = read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

551

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

556

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

561

tmp = read32(iirControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

580

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

589

tmp = read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

599

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

603

tmp = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

608

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

613

tmp = read32(iirControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

62

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

65

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

656

uint32 buffer = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

676

buffer = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

681

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

682

write32(rxControl, read32(rxControl) | FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

683

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

687

buffer = read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

694

write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

695

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

696

write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

697

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

714

write32(rxControl, read32(rxControl)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

716

read32(rxControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

718

write32(txControl, read32(txControl) | (0x3 << 8));

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

719

read32(txControl);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

75

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

78

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

87

return (read32(FDI_TX_CTL(fPipeIndex)) & FDI_TX_PLL_ENABLED) != 0;

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

96

uint32 value = read32(targetRegister);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

109

write32(targetRegister, (read32(targetRegister) & ~PANEL_FITTER_ENABLED)

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

111

read32(targetRegister);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

51

uint32 fitCtl = read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

75

return (read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL)

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

87

TRACE("%s: PCH_PANEL_FITTER_CONTROL, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL));

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

88

TRACE("%s: PCH_PANEL_FITTER_WINDOW_POS, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_POS));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

124

return (read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

132

uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

148

read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

154

write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

210

read32(DDI_SKL_TRANS_CONF_A + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

212

read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

213

uint32 value = (read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset) & PIPE_DDI_MODESEL_MASK)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

238

TRACE("%s: FDI/PIPE M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

239

TRACE("%s: FDI/PIPE N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

240

TRACE("%s: FDI/PIPE M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

241

TRACE("%s: FDI/PIPE N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

291

TRACE("%s: FDI/PIPE M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

292

TRACE("%s: FDI/PIPE N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

293

TRACE("%s: FDI/PIPE M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

294

TRACE("%s: FDI/PIPE N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

419

write32(pllControl, read32(pllControl) & ~DISPLAY_PLL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

42

write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

45

write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

49

write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

504

read32(pllControl);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

509

read32(pllControl);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

518

uint32 pllSel = read32(SNB_DPLL_SEL);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

52

write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

556

uint32 portSel = read32(SKL_DPLL_CTRL2);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

581

read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

583

read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

586

portSel = read32(SKL_DPLL_CTRL1);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

601

read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

602

read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

607

if (read32(SKL_DPLL_STATUS) & (1 << (*pllSel * 8))) {

src/add-ons/accelerants/intel_extreme/Pipes.cpp

613

read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

615

read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

620

TRACE("Skylake DPLL_CTRL1: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL1));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

621

TRACE("Skylake DPLL_CTRL2: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL2));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

622

TRACE("Skylake DPLL_STATUS: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_STATUS));

src/add-ons/accelerants/intel_extreme/Pipes.cpp

636

write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

638

write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

648

write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

653

write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

658

read32(INTEL_DISPLAY_A_BASE);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1056

write32(_PortRegister(), (read32(_PortRegister())

src/add-ons/accelerants/intel_extreme/Ports.cpp

1087

write32(panelControl, read32(panelControl) | PANEL_REGISTER_UNLOCK);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1115

uint32 portState = read32(_PortRegister());

src/add-ons/accelerants/intel_extreme/Ports.cpp

1141

uint32 registerValue = read32(_PortRegister());

src/add-ons/accelerants/intel_extreme/Ports.cpp

1227

read32(panelControl) & ~PANEL_CONTROL_POWER_TARGET_ON);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1228

read32(panelControl);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1292

uint32 lvds = read32(_PortRegister())

src/add-ons/accelerants/intel_extreme/Ports.cpp

1333

read32(_PortRegister());

src/add-ons/accelerants/intel_extreme/Ports.cpp

1353

read32(panelControl) | PANEL_CONTROL_POWER_TARGET_ON);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1354

read32(panelControl);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1369

uint32 panelFitterControl = read32(INTEL_PANEL_FIT_CONTROL);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1382

uint32 panelFitterControl = read32(INTEL_PANEL_FIT_CONTROL);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1560

if ((read32(portRegister) & DISPLAY_MONITOR_PORT_ENABLED) == 0)

src/add-ons/accelerants/intel_extreme/Ports.cpp

1621

if (((read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_SNB_PIPE_MASK)

src/add-ons/accelerants/intel_extreme/Ports.cpp

1629

uint32 Pipe = (read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_IVB_PIPE_MASK)

src/add-ons/accelerants/intel_extreme/Ports.cpp

1657

if ((read32(INTEL_TRANSCODER_A_DP_CTL + (Transcoder << 12)) & INTEL_TRANS_DP_PORT_MASK) ==

src/add-ons/accelerants/intel_extreme/Ports.cpp

168

uint32 portState = read32(portRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

1758

if ((read32(portRegister) & DISPLAY_MONITOR_PORT_ENABLED) == 0) {

src/add-ons/accelerants/intel_extreme/Ports.cpp

1851

TRACE("%s: DP M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1852

TRACE("%s: DP N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1853

TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1854

TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1895

TRACE("%s: DP M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1896

TRACE("%s: DP N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1897

TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1898

TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1924

TRACE("%s: DP M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1925

TRACE("%s: DP N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1926

TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1927

TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

1930

(read32(INTEL_TRANSCODER_A_DP_CTL + fPipeOffset) & INTEL_TRANS_DP_BPC_MASK) >> INTEL_TRANS_DP_COLOR_SHIFT;

src/add-ons/accelerants/intel_extreme/Ports.cpp

1950

uint32 lanes = ((read32(_PortRegister()) & INTEL_DISP_PORT_WIDTH_MASK) >> INTEL_DISP_PORT_WIDTH_SHIFT) + 1;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2004

TRACE("%s: DP M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2005

TRACE("%s: DP N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2006

TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2007

TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

202

read32(portRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2086

(read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_EDP_PLL_FREQ_MASK) >> INTEL_DISP_EDP_PLL_FREQ_SHIFT;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2100

(read32(INTEL_DISPLAY_A_PIPE_CONTROL) & INTEL_PIPE_BPC_MASK) >> INTEL_PIPE_COLOR_SHIFT;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2119

((read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORT_WIDTH_MASK) >> INTEL_DISP_PORT_WIDTH_SHIFT) + 1;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2168

if ((read32(portRegister) & DISPLAY_MONITOR_PORT_DETECTED) == 0) {

src/add-ons/accelerants/intel_extreme/Ports.cpp

2248

uint32 state = read32(portRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2251

read32(portRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2341

if ((read32(DDI_BUF_CTL_A) & DDI_A_4_LANES) != 0) {

src/add-ons/accelerants/intel_extreme/Ports.cpp

2390

pipeState = read32(PIPE_DDI_FUNC_CTL_EDP);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2421

pipeState = read32(PIPE_DDI_FUNC_CTL_B);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2424

pipeState = read32(PIPE_DDI_FUNC_CTL_C);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2427

pipeState = read32(PIPE_DDI_FUNC_CTL_A);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2454

pipeState = read32(pipeReg);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2479

linkBandwidth = (read32(SKL_DPLL_CTRL1) >> (1 + 6 * pllSel)) & SKL_DPLL_DP_LINKRATE_MASK;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2525

TRACE("%s: DDI M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2526

TRACE("%s: DDI N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2527

TRACE("%s: DDI M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2528

TRACE("%s: DDI N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2530

uint32 pipeFunc = read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset);

src/add-ons/accelerants/intel_extreme/Ports.cpp

2597

TRACE("%s: DDI M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2598

TRACE("%s: DDI N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2599

TRACE("%s: DDI M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2600

TRACE("%s: DDI N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));

src/add-ons/accelerants/intel_extreme/Ports.cpp

2741

uint32 config = read32(TGL_DPCLKA_CFGCR0);

src/add-ons/accelerants/intel_extreme/Ports.cpp

312

uint32 portState = read32(_PortRegister());

src/add-ons/accelerants/intel_extreme/Ports.cpp

333

pipeState = read32(PIPE_DDI_FUNC_CTL_A);

src/add-ons/accelerants/intel_extreme/Ports.cpp

336

pipeState = read32(PIPE_DDI_FUNC_CTL_B);

src/add-ons/accelerants/intel_extreme/Ports.cpp

339

pipeState = read32(PIPE_DDI_FUNC_CTL_C);

src/add-ons/accelerants/intel_extreme/Ports.cpp

342

pipeState = read32(PIPE_DDI_FUNC_CTL_EDP);

src/add-ons/accelerants/intel_extreme/Ports.cpp

370

uint32 value = read32(ioRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

390

value = read32(ioRegister) & I2C_RESERVED;

src/add-ons/accelerants/intel_extreme/Ports.cpp

412

read32(ioRegister);

src/add-ons/accelerants/intel_extreme/Ports.cpp

52

if ((read32(address) & mask) != 0)

src/add-ons/accelerants/intel_extreme/Ports.cpp

602

uint32 value = read32(ICL_PWR_WELL_CTL_AUX2);

src/add-ons/accelerants/intel_extreme/Ports.cpp

66

if ((read32(address) & mask) == 0)

src/add-ons/accelerants/intel_extreme/Ports.cpp

81

status = read32(address);

src/add-ons/accelerants/intel_extreme/Ports.cpp

863

while ((read32(channelControl) & INTEL_DP_AUX_CTL_BUSY) != 0) {

src/add-ons/accelerants/intel_extreme/Ports.cpp

945

uint32 data = read32(channelData[i / 4]);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

289

int32 initialState = read32(DPLL_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

293

int32 oldDCO = read32(DPLL_CFGCR0);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

294

int32 oldDividers = read32(DPLL_CFGCR1);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

306

write32(DPLL_ENABLE, read32(DPLL_ENABLE) & ~TGL_DPLL_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

307

while ((read32(DPLL_ENABLE) & TGL_DPLL_LOCK) != 0);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

311

write32(DPLL_ENABLE, read32(DPLL_ENABLE) | TGL_DPLL_POWER_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

314

while ((read32(DPLL_ENABLE) & TGL_DPLL_POWER_STATE) == 0);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

318

write32(DPLL_SPREAD_SPECTRUM, read32(DPLL_SPREAD_SPECTRUM) & ~TGL_DPLL_SSC_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

330

read32(DPLL_CFGCR1);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

335

write32(DPLL_ENABLE, read32(DPLL_ENABLE) | TGL_DPLL_ENABLE);

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

336

TRACE("DPLL_ENABLE(%" B_PRIx32 ") = %" B_PRIx32 "\n", DPLL_ENABLE, read32(DPLL_ENABLE));

src/add-ons/accelerants/intel_extreme/TigerLakePLL.cpp

339

while ((read32(DPLL_ENABLE) & TGL_DPLL_LOCK) == 0);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

254

TRACE("adpa: %08" B_PRIx32 "\n", read32(INTEL_ANALOG_PORT));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

256

", dovc: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_PORT_A),

src/add-ons/accelerants/intel_extreme/accelerant.cpp

257

read32(INTEL_DIGITAL_PORT_B), read32(INTEL_DIGITAL_PORT_C));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

258

TRACE("lvds: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_LVDS_PORT));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

260

TRACE("dp_a: %08" B_PRIx32 "\n", read32(INTEL_DISPLAY_PORT_A));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

261

TRACE("dp_b: %08" B_PRIx32 "\n", read32(INTEL_DISPLAY_PORT_B));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

262

TRACE("dp_c: %08" B_PRIx32 "\n", read32(INTEL_DISPLAY_PORT_C));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

263

TRACE("dp_d: %08" B_PRIx32 "\n", read32(INTEL_DISPLAY_PORT_D));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

264

TRACE("tra_dp: %08" B_PRIx32 "\n", read32(INTEL_TRANSCODER_A_DP_CTL));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

265

TRACE("trb_dp: %08" B_PRIx32 "\n", read32(INTEL_TRANSCODER_B_DP_CTL));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

266

TRACE("trc_dp: %08" B_PRIx32 "\n", read32(INTEL_TRANSCODER_C_DP_CTL));

src/add-ons/accelerants/intel_extreme/accelerant.cpp

277

read32(INTEL_DSPCLK_GATE_D) | PCH_GMBUSUNIT_CLK_GATE_DIS);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

278

read32(INTEL_DSPCLK_GATE_D);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

281

read32(INTEL_GEN9_CLKGATE_DIS_4) | BXT_GMBUSUNIT_CLK_GATE_DIS);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

282

read32(INTEL_GEN9_CLKGATE_DIS_4);

src/add-ons/accelerants/intel_extreme/accelerant.cpp

69

data = read32(i);

src/add-ons/accelerants/intel_extreme/cursor.cpp

65

int32 x = read32(INTEL_CURSOR_POSITION);

src/add-ons/accelerants/intel_extreme/dpms.cpp

102

read32(INTEL_DISPLAY_A_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

106

pll = read32(INTEL_DISPLAY_B_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

110

read32(INTEL_DISPLAY_B_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

113

read32(INTEL_DISPLAY_B_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

116

read32(INTEL_DISPLAY_B_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

142

write32(INTEL_ANALOG_PORT, (read32(INTEL_ANALOG_PORT)

src/add-ons/accelerants/intel_extreme/dpms.cpp

150

write32(INTEL_DIGITAL_PORT_B, (read32(INTEL_DIGITAL_PORT_B)

src/add-ons/accelerants/intel_extreme/dpms.cpp

160

write32(INTEL_DISPLAY_A_PLL, read32(INTEL_DISPLAY_A_PLL)

src/add-ons/accelerants/intel_extreme/dpms.cpp

162

write32(INTEL_DISPLAY_B_PLL, read32(INTEL_DISPLAY_B_PLL)

src/add-ons/accelerants/intel_extreme/dpms.cpp

165

read32(INTEL_DISPLAY_B_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

174

read32(INTEL_DISPLAY_A_BASE);

src/add-ons/accelerants/intel_extreme/dpms.cpp

41

read32(INTEL_DISPLAY_A_BASE);

src/add-ons/accelerants/intel_extreme/dpms.cpp

56

uint32 control = read32(controlRegister);

src/add-ons/accelerants/intel_extreme/dpms.cpp

67

panelStatus = read32(statusRegister);

src/add-ons/accelerants/intel_extreme/dpms.cpp

79

panelStatus = read32(statusRegister);

src/add-ons/accelerants/intel_extreme/dpms.cpp

92

uint32 pll = read32(INTEL_DISPLAY_A_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

96

read32(INTEL_DISPLAY_A_PLL);

src/add-ons/accelerants/intel_extreme/dpms.cpp

99

read32(INTEL_DISPLAY_A_PLL);

src/add-ons/accelerants/intel_extreme/engine.cpp

122

uint32 head = read32(fRingBuffer.register_base + RING_BUFFER_HEAD)

src/add-ons/accelerants/intel_extreme/engine.cpp

255

head = read32(ring.register_base + RING_BUFFER_HEAD)

src/add-ons/accelerants/intel_extreme/engine.cpp

257

tail = read32(ring.register_base + RING_BUFFER_TAIL)

src/add-ons/accelerants/intel_extreme/mode.cpp

148

read32(INTEL_DISPLAY_A_OFFSET_HAS + offset);

src/add-ons/accelerants/intel_extreme/mode.cpp

153

read32(INTEL_DISPLAY_A_BASE + offset);

src/add-ons/accelerants/intel_extreme/mode.cpp

156

read32(INTEL_DISPLAY_A_SURFACE + offset);

src/add-ons/accelerants/intel_extreme/mode.cpp

161

read32(INTEL_DISPLAY_A_BASE + offset);

src/add-ons/accelerants/intel_extreme/mode.cpp

476

read32(INTEL_VGA_DISPLAY_CONTROL);

src/add-ons/accelerants/intel_extreme/mode.cpp

622

uint32_t period = read32(intel_get_backlight_register(true));

src/add-ons/accelerants/intel_extreme/mode.cpp

629

uint32_t period = read32(intel_get_backlight_register(true)) >> 16;

src/add-ons/accelerants/intel_extreme/mode.cpp

637

uint32 tmp = read32(intel_get_backlight_register(true));

src/add-ons/accelerants/intel_extreme/mode.cpp

694

period = read32(intel_get_backlight_register(true));

src/add-ons/accelerants/intel_extreme/mode.cpp

695

duty = read32(intel_get_backlight_register(false));

src/add-ons/accelerants/intel_extreme/mode.cpp

697

uint32 tmp = read32(intel_get_backlight_register(true));

src/add-ons/accelerants/intel_extreme/mode.cpp

705

duty = read32(intel_get_backlight_register(false)) & 0xffff;

src/add-ons/accelerants/intel_extreme/overlay.cpp

251

__func__, read32(INTEL_OVERLAY_UPDATE),

src/add-ons/accelerants/intel_extreme/overlay.cpp

252

read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),

src/add-ons/accelerants/intel_extreme/overlay.cpp

253

*(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168),

src/add-ons/accelerants/intel_extreme/overlay.cpp

254

read32(0x2024));

src/add-ons/accelerants/intel_extreme/overlay.cpp

273

__func__, read32(INTEL_OVERLAY_UPDATE),

src/add-ons/accelerants/intel_extreme/overlay.cpp

274

read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),

src/add-ons/accelerants/intel_extreme/overlay.cpp

276

read32(0x30168), read32(0x2024));

src/add-ons/accelerants/intel_extreme/pll.cpp

195

return ((read32(INTEL_DIGITAL_LVDS_PORT) & LVDS_CLKB_POWER_MASK)

src/add-ons/accelerants/intel_extreme/pll.cpp

492

uint32 clkRef = read32(PCH_DREF_CONTROL);

src/add-ons/accelerants/intel_extreme/pll.cpp

523

read32(PCH_DREF_CONTROL);

src/add-ons/accelerants/intel_extreme/pll.cpp

525

__func__, read32(PCH_DREF_CONTROL));

src/add-ons/accelerants/intel_extreme/pll.cpp

540

read32(PCH_DREF_CONTROL);

src/add-ons/accelerants/intel_extreme/pll.cpp

542

__func__, read32(PCH_DREF_CONTROL));

src/add-ons/accelerants/intel_extreme/pll.cpp

549

read32(PCH_DREF_CONTROL);

src/add-ons/accelerants/intel_extreme/pll.cpp

551

__func__, read32(PCH_DREF_CONTROL));

src/add-ons/accelerants/intel_extreme/pll.cpp

560

read32(PCH_DREF_CONTROL);

src/add-ons/accelerants/intel_extreme/pll.cpp

562

__func__, read32(PCH_DREF_CONTROL));

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

724

info.gtt_physical_base = read32(info.registers

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

833

read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL);

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

839

read32(sInfo.gtt_base + sInfo.gtt_entries - 1);

src/add-ons/kernel/busses/agp_gart/intel_gart.cpp

903

read32(sInfo.gtt_base + sInfo.gtt_entries - 1);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

118

status = read32(bus->registers + PCH_IC_STATUS);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

133

read32(bus->registers + PCH_IC_CON) & ~PCH_IC_CON_10BIT_ADDR_MASTER);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

137

read32(bus->registers + PCH_IC_CLR_INTR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

141

read32(bus->registers + PCH_IC_CLR_INTR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

150

- read32(bus->registers + PCH_IC_TXFLR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

170

- read32(bus->registers + PCH_IC_TXFLR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

206

uint32 rxBytes = read32(bus->registers + PCH_IC_RXFLR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

214

uint32 read = read32(bus->registers + PCH_IC_DATA_CMD);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

227

- read32(bus->registers + PCH_IC_TXFLR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

31

if ((read32(bus->registers + PCH_IC_ENABLE_STATUS) & 1) == status)

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

413

uint32 version = read32(bus->registers + PCH_IC_COMP_VERSION);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

417

bus->capabilities = read32(bus->registers + PCH_SUP_CAPABLITIES);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

433

bus->ss_hcnt = read32(bus->registers + PCH_IC_SS_SCL_HCNT);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

435

bus->ss_lcnt = read32(bus->registers + PCH_IC_SS_SCL_LCNT);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

437

bus->fs_hcnt = read32(bus->registers + PCH_IC_FS_SCL_HCNT);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

439

bus->fs_lcnt = read32(bus->registers + PCH_IC_FS_SCL_LCNT);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

441

bus->sda_hold_time = read32(bus->registers + PCH_IC_SDA_HOLD);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

457

uint32 reg = read32(bus->registers + PCH_IC_COMP_VERSION);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

46

uint32 enable = read32(bus->registers + PCH_IC_ENABLE);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

465

uint32 reg = read32(bus->registers + PCH_IC_COMP_PARAM1);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

481

read32(bus->registers + PCH_IC_CLR_INTR);

src/add-ons/kernel/busses/i2c/pch/pch_i2c.cpp

50

uint32 status = read32(bus->registers + PCH_IC_INTR_STAT);

src/add-ons/kernel/busses/random/ccp/ccp.cpp

32

uint32 lowValue = read32(bus->registers + CCP_REG_TRNG);

src/add-ons/kernel/busses/random/ccp/ccp.cpp

33

uint32 highValue = read32(bus->registers + CCP_REG_TRNG);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

122

value = read32(info, INTEL_DISPLAY_A_HTOTAL + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

125

value = read32(info, INTEL_DISPLAY_A_HBLANK + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

128

value = read32(info, INTEL_DISPLAY_A_HSYNC + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

131

value = read32(info, INTEL_DISPLAY_A_VTOTAL + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

134

value = read32(info, INTEL_DISPLAY_A_VBLANK + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

137

value = read32(info, INTEL_DISPLAY_A_VSYNC + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

140

value = read32(info, INTEL_DISPLAY_A_PIPE_SIZE + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

147

value = read32(info, INTEL_TRANSCODER_A_HTOTAL + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

150

value = read32(info, INTEL_TRANSCODER_A_HBLANK + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

153

value = read32(info, INTEL_TRANSCODER_A_HSYNC + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

156

value = read32(info, INTEL_TRANSCODER_A_VTOTAL + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

159

value = read32(info, INTEL_TRANSCODER_A_VBLANK + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

162

value = read32(info, INTEL_TRANSCODER_A_VSYNC + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

165

value = read32(info, INTEL_TRANSCODER_A_IMAGE_SIZE + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

172

value = read32(info, INTEL_DISPLAY_A_CONTROL + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

174

value = read32(info, INTEL_DISPLAY_A_BASE + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

176

value = read32(info, INTEL_DISPLAY_A_BYTES_PER_ROW + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

178

value = read32(info, INTEL_DISPLAY_A_SURFACE + pipeOffset);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

85

uint32 oldValue = read32(info, reg);

src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp

93

value = read32(info, reg);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

107

return enable ? 0 : read32(info, GEN11_GFX_MSTR_IRQ);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

115

return enable ? 0 : read32(info, PCH_MASTER_INT_CTL_BDW);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

129

uint32 identity = read32(info, regIdentity);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

140

uint32 identity = read32(info, regIdentity);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

151

uint32 identity = read32(info, regIdentity);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

162

uint32 iir = read32(info, GEN8_DE_PORT_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

171

uint32 iir = read32(info, GEN11_DE_HPD_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

181

uint32 iir = read32(info, SDEIIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

186

uint32 ddiHotplug = read32(info, SHOTPLUG_CTL_DDI);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

190

uint32 tcHotplug = read32(info, SHOTPLUG_CTL_TC);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

293

const uint32 interrupt = read32(info, regIdentity);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

332

const uint32 identity = read32(info, regIdentity);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

377

handled = gen8_handle_interrupts(info, read32(info, GEN11_DISPLAY_INT_CTL));

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

486

read32(info, SDEIIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

489

read32(info, SDEIMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

496

read32(info, GEN8_DE_PORT_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

499

read32(info, GEN8_DE_PORT_IMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

501

read32(info, GEN8_DE_MISC_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

504

read32(info, GEN8_DE_MISC_IMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

506

read32(info, GEN11_GU_MISC_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

509

read32(info, GEN11_GU_MISC_IMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

511

read32(info, GEN11_DE_HPD_IIR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

515

read32(info, GEN11_DE_HPD_IMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

523

read32(info, SDEIMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

525

read32(info, SDEIMR);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

527

uint32 ctl = read32(info, SHOTPLUG_CTL_DDI);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

534

ctl = read32(info, SHOTPLUG_CTL_TC);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

787

(read32(info, ICL_DSSM) & ICL_DSSM_REF_FREQ_MASK) >> ICL_DSSM_REF_FREQ_SHIFT;

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

867

info.shared_info->fdi_link_frequency = (read32(info, FDI_PLL_BIOS_0)

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

876

info.shared_info->hraw_clock = (read32(info, PCH_RAWCLK_FREQ)

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

886

uint32 lcpll = read32(info, LCPLL_CTL);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

889

else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0)

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

900

uint32 lcpll = read32(info, LCPLL_CTL);

src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp

903

else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0)

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

100

uint32 gtPerfStatus = read32(info, INTEL6_GT_PERF_STATUS);

src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp

99

uint32 rpStateCapacity = read32(info, INTEL6_RP_STATE_CAP);

src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp

84

uint32 oldValue = read32(info.registers + reg);

src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp

91

value = read32(info.registers + reg);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

330

uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

331

uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

332

uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

334

= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

335

uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

398

uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

399

uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

400

uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

401

uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

403

= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

404

uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

471

uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

472

uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

473

uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

474

uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

476

= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

477

uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

478

uint32 general_pwrmgt = read32(info.registers + R600_GENERAL_PWRMGT);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

480

= read32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

482

= read32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

484

= read32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

486

= read32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

488

= read32(info.registers + R600_LOWER_GPIO_ENABLE);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

580

uint32 sepromControl = read32(info.registers + RADEON_SEPROM_CNTL1);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

581

uint32 viphControl = read32(info.registers + RADEON_VIPH_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

582

uint32 busControl = read32(info.registers + RV370_BUS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

583

uint32 d1vgaControl = read32(info.registers + AVIVO_D1VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

584

uint32 d2vgaControl = read32(info.registers + AVIVO_D2VGA_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

586

= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

587

uint32 gpioPadA = read32(info.registers + RADEON_GPIOPAD_A);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

588

uint32 gpioPadEN = read32(info.registers + RADEON_GPIOPAD_EN);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

589

uint32 gpioPadMask = read32(info.registers + RADEON_GPIOPAD_MASK);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

713

= read32(info.registers + CONFIG_MEMSIZE_TAHITI) * 1024;

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

719

= read32(info.registers + CONFIG_MEMSIZE) * 1024;

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

726

= read32(info.registers + CONFIG_MEMSIZE) / 1024;

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

732

= read32(info.registers + CONFIG_MEMSIZE) / 1024;

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

738

uint32 tom = read32(info.registers + RADEON_NB_TOM);

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

745

= read32(info.registers + RADEON_CONFIG_MEMSIZE);

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

30

rawTemp = (read32(info.registers + SI_CG_MULT_THERMAL_STATUS)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

40

uint32 offset = (read32(info.registers + EVERGREEN_CG_THERMAL_CTRL)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

42

rawTemp = (read32(info.registers + EVERGREEN_CG_TS0_STATUS)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

53

uint32 rawTemp = read32(info.registers + EVERGREEN_CG_THERMAL_STATUS)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

59

rawTemp = (read32(info.registers + EVERGREEN_CG_MULT_THERMAL_STATUS)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

74

rawTemp = (read32(info.registers + R700_CG_MULT_THERMAL_STATUS)

src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp

88

rawTemp = (read32(info.registers + R600_CG_THERMAL_STATUS)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

136

ack = read32(device->reg_base + WB_SIO) & WB_SIO_MII_DATAOUT;

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

162

if (read32(device->reg_base + WB_SIO) & WB_SIO_MII_DATAOUT)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

257

#define EEPROM_DELAY(x) read32(x->reg_base + WB_SIO)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

339

if (read32(device->reg_base + WB_SIO) & WB_SIO_EE_DATAOUT)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

47

read32(device->reg_base + WB_SIO) | x)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

51

read32(device->reg_base + WB_SIO) & ~x)

src/add-ons/kernel/drivers/network/ether/wb840/interface.c

53

#define MII_DELAY(x) read32(x->reg_base + WB_SIO)

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

221

if (!(read32(device->reg_base + WB_BUSCTL) & WB_BUSCTL_RESET))

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

239

if (read32(cfgAddress) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

243

if ((read32(device->reg_base + WB_ISR) & WB_ISR_TX_IDLE) &&

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

244

(read32(device->reg_base + WB_ISR) & WB_ISR_RX_IDLE))

src/add-ons/kernel/drivers/network/ether/wb840/wb840.c

398

status = read32(device->reg_base + WB_ISR);

src/add-ons/kernel/drivers/network/ether/wb840/wb840.h

486

#define WB_SETBIT(reg, x) write32(reg, read32(reg) | x)

src/add-ons/kernel/drivers/network/ether/wb840/wb840.h

487

#define WB_CLRBIT(reg, x) write32(reg, read32(reg) & ~x)

src/add-ons/kernel/file_systems/fat/support.cpp

367

sectorsPerFat = read32(bootsector, 0x24);

src/add-ons/kernel/file_systems/fat/support.cpp

370

totalSectors = read32(bootsector, 0x20);

src/system/boot/loader/file_systems/fat/Volume.cpp

122

fSectorsPerFat = read32(buf,0x24);

src/system/boot/loader/file_systems/fat/Volume.cpp

123

fTotalSectors = read32(buf,0x20);

src/system/boot/loader/file_systems/fat/Volume.cpp

128

fRootDirCluster = read32(buf,0x2c);

src/system/boot/loader/file_systems/fat/Volume.cpp

235

next = read32(buf, offset);

src/system/boot/loader/file_systems/fat/Volume.cpp

292

uint32 value = read32(buffer, offset & blockOffsetMask);

src/system/boot/loader/file_systems/fat/Volume.cpp

386

int32 freeClusters = read32(buffer, 0x1e8);