out8
out8(value, mapped_io_addr);
out8(value, mapped_io_addr);
out8(value, mapped_io_addr);
out8(value, mapped_io_addr);
out8(value, mapped_io_addr);
out8(value, mapped_io_addr);
out8(value, PCI_MECH1_DATA_PORT + (offset & 3));
out8(0x00, 0xCFB);
out8(0x00, 0xCF8);
out8(0x00, 0xCFA);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT);
out8(0, PCI_MECH2_ENABLE_PORT);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT);
out8(value, PCI_MECH2_CONFIG_PORT(device, offset));
out8(0, PCI_MECH2_ENABLE_PORT);
out8(data, port);
out8(select | PIT_ACCESS_LOW_THEN_HIGH_BYTE | PIT_MODE_INTERRUPT_ON_0
out8(0xff, channelPort);
out8(0xff, channelPort);
out8(select | PIT_ACCESS_LATCH_COUNTER, PIT_CONTROL);
out8(select | PIT_ACCESS_LATCH_COUNTER, PIT_CONTROL);
out8(control, PIT_CHANNEL_2_CONTROL);
out8(in8(PIT_CHANNEL_2_CONTROL) & ~PIT_CHANNEL_2_GATE_HIGH,
out8(0x80, sSerialBasePort + SERIAL_LINE_CONTROL);
out8(divisor & 0xf, sSerialBasePort + SERIAL_DIVISOR_LATCH_LOW);
out8(divisor >> 8, sSerialBasePort + SERIAL_DIVISOR_LATCH_HIGH);
out8(3, sSerialBasePort + SERIAL_LINE_CONTROL);
out8(c, sSerialBasePort + SERIAL_TRANSMIT_BUFFER);
out8(0xfe, 0x64);
out8(firstIndex, VGA_COLOR_WRITE_MODE);
out8(palette[i * 3 + 0] >> 2, VGA_COLOR_DATA);
out8(palette[i * 3 + 1] >> 2, VGA_COLOR_DATA);
out8(palette[i * 3 + 2] >> 2, VGA_COLOR_DATA);
out8(0x30, VGA_ATTRIBUTE_WRITE);
out8(mode, VGA_ATTRIBUTE_WRITE);
out8(0xfe, 0x64);
out8(c, sSerialBasePort + SERIAL_TRANSMIT_BUFFER);
out8(0x80, sSerialBasePort + SERIAL_LINE_CONTROL); /* set divisor latch access bit */
out8(divisor & 0xf, sSerialBasePort + SERIAL_DIVISOR_LATCH_LOW);
out8(divisor >> 8, sSerialBasePort + SERIAL_DIVISOR_LATCH_HIGH);
out8(3, sSerialBasePort + SERIAL_LINE_CONTROL); /* 8N1 */
out8(0x0a, CMOS_ADDR_PORT);
out8(addr, CMOS_ADDR_PORT);
out8(addr, CMOS_ADDR_PORT);
out8(data, CMOS_DATA_PORT);
out8(PIC_NON_SPECIFIC_EOI, PIC_SLAVE_CONTROL);
out8(PIC_NON_SPECIFIC_EOI, PIC_MASTER_CONTROL);
out8(in8(PIC_MASTER_MASK) & ~(1 << num), PIC_MASTER_MASK);
out8(in8(PIC_SLAVE_MASK) & ~(1 << (num - PIC_SLAVE_INT_BASE)), PIC_SLAVE_MASK);
out8(in8(PIC_MASTER_MASK) | (1 << num), PIC_MASTER_MASK);
out8(in8(PIC_SLAVE_MASK) | (1 << (num - PIC_SLAVE_INT_BASE)), PIC_SLAVE_MASK);
out8(value, PIC_MASTER_TRIGGER_MODE);
out8(value, PIC_SLAVE_TRIGGER_MODE);
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_MASTER_INIT1);
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_SLAVE_INIT1);
out8(ARCH_INTERRUPT_BASE, PIC_MASTER_INIT2);
out8(ARCH_INTERRUPT_BASE + PIC_SLAVE_INT_BASE, PIC_SLAVE_INIT2);
out8(PIC_INIT3_IR2_IS_SLAVE, PIC_MASTER_INIT3);
out8(PIC_INIT3_SLAVE_ID2, PIC_SLAVE_INIT3);
out8(PIC_INIT4_x86_MODE, PIC_MASTER_INIT4);
out8(PIC_INIT4_x86_MODE, PIC_SLAVE_INIT4);
out8(0xfb, PIC_MASTER_MASK); // Mask off all interrupts (except slave pic line IRQ 2).
out8(0xff, PIC_SLAVE_MASK); // Mask off interrupts on the slave.
out8(0xf8, PIC_MASTER_TRIGGER_MODE);
out8(0xde, PIC_SLAVE_TRIGGER_MODE);
out8(0xff, PIC_MASTER_MASK);
out8(0xff, PIC_SLAVE_MASK);
out8(PIC_CONTROL3 | PIC_CONTROL3_READ_ISR, PIC_MASTER_CONTROL);
out8(PIC_CONTROL3 | PIC_CONTROL3_READ_IRR, PIC_MASTER_CONTROL);
out8(PIT_SELCH0 | PIT_RWBOTH | PIT_MD_INTON0, PIT_CTRL);
out8(nextEventClocks & 0xff, PIT_CNT0);
out8((nextEventClocks >> 8) & 0xff, PIT_CNT0);
void WriteReg(uint32 reg, uint8 v) { out8(v, fBase + reg); };
void WriteReg(uint32 reg, uint8 v) { out8((uint8)reg,fBase+1); out8(v,fBase+3); };
out8(val, reg);
out8(val, reg);
out8(val, reg);
out8(0x0a, fBase+1);
out8((uint8)reg,fBase+1);