jme_dev
error = resource_int_value(device_get_name(sc->jme_dev),
device_get_unit(sc->jme_dev), "process_limit",
device_printf(sc->jme_dev,
error = resource_int_value(device_get_name(sc->jme_dev),
device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
device_printf(sc->jme_dev,
error = resource_int_value(device_get_name(sc->jme_dev),
device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
device_printf(sc->jme_dev,
error = resource_int_value(device_get_name(sc->jme_dev),
device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
device_printf(sc->jme_dev,
error = resource_int_value(device_get_name(sc->jme_dev),
device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
device_printf(sc->jme_dev,
error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev, "4GB boundary crossed, "
error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
device_printf(sc->jme_dev, "could not allocate DMA'able "
device_printf(sc->jme_dev, "could not load DMA'able memory "
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
device_printf(sc->jme_dev, "establishing link failed, "
if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) {
pmstat = pci_read_config(sc->jme_dev,
pci_write_config(sc->jme_dev,
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
device_printf(sc->jme_dev,
device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
device_printf(sc->jme_dev, "stopping recevier timeout!\n");
struct jme_dev *sp;
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
device_printf(sc->jme_dev, "EEPROM read timeout!\n");
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
device_printf(sc->jme_dev, "eFuse autoload timed out.\n");
device_printf(sc->jme_dev,
pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
sc->jme_dev = dev;
device_printf(sc->jme_dev,
device_printf(sc->jme_dev,
device_get_nameunit(sc->jme_dev));
ctx = device_get_sysctl_ctx(sc->jme_dev);
child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
device_t jme_dev;