iwm_write_prph
iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);
iwm_write_prph(sc, IWM_WFPM_CTRL_REG, hw_step);
iwm_write_prph(sc, reg, val);
iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0);
iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
iwm_write_prph(sc, IWM_UREG_CHICK,
iwm_write_prph(sc, IWM_UREG_CHICK, IWM_UREG_CHICK_MSIX_ENABLE);
iwm_write_prph(sc, IWM_SCD_TXFACT, 0);
iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG,
iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0);
iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, 0);
iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_WIDX, 0);
iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_RIDX, 0);
iwm_write_prph(sc, IWM_RFH_Q0_URBDCB_WIDX, 0);
iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG,
iwm_write_prph(sc, IWM_RFH_GEN_CFG,
iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, enabled);
iwm_write_prph(sc, IWM_SCD_TXFACT, 0);
iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0);
iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
iwm_write_prph(sc, IWM_SCD_EN_CTRL,
iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10);
iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0);
iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff);
void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t);
iwm_write_prph(sc, IWM_RELEASE_CPU_RESET,