BIT_27
#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
#define RX_TRUNC_ON BIT_27 /* enable packet truncation */
#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */
#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */
#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */