BIT_11
#define GLB_GPIO_TEST_SEL_BASE BIT_11
#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11
#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */
#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */
#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */
#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */
#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */
#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */
#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */
#define GM_GPSR_PAUSE BIT_11 /* Pause State */
#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */
#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */
#define PCI_PATCH_DIR_3 BIT_11
#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */
#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */