BIT_0
#define I2C_STOP BIT_0 /* Interrupt I2C transfer */
#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
#define I2C_CLK BIT_0 /* I2C Clock Port */
#define BSC_STOP BIT_0 /* Stop Blink Source Counter */
#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */
#define BSC_T_STEP BIT_0 /* Test step */
#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */
#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */
#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */
#define BMU_RST_SET BIT_0 /* Set BMU Reset */
#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
#define RB_PC_INC BIT_0 /* Packet Counter Increment */
#define RB_RP_INC BIT_0 /* Read Pointer Increment */
#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */
#define WOL_CTL_DIS_PATTERN_UNIT BIT_0
#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */
#define PHY_M_PS_JABBER BIT_0 /* Jabber */
#define PHY_M_IS_JABBER BIT_0 /* Jabber */
#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */
#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */
#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */
#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */
#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
#define GPC_RST_SET BIT_0 /* Set GPHY Reset */
#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */
#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
#define CS_RST_SET BIT_0 /* Set Software Reset */
#define LED_STAT_OFF BIT_0 /* Status LED Off */
#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */
#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */
#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */
#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */
#define TIM_T_STEP BIT_0 /* Test step */
#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */
#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */