fwohcireg_t
fwohcireg_t stat;
fwohcireg_t cntl;
fwohcireg_t cntl_clr;
fwohcireg_t dummy0;
fwohcireg_t cmd;
fwohcireg_t match;
fwohcireg_t dummy1;
fwohcireg_t dummy2;
fwohcireg_t dummy3;
fwohcireg_t cntl;
fwohcireg_t cntl_clr;
fwohcireg_t dummy0;
fwohcireg_t cmd;
fwohcireg_t ver; /* Version No. 0x0 */
fwohcireg_t guid; /* GUID_ROM No. 0x4 */
fwohcireg_t retry; /* AT retries 0x8 */
fwohcireg_t csr_data; /* CSR data 0xc */
fwohcireg_t csr_cmp; /* CSR compare 0x10 */
fwohcireg_t csr_cntl; /* CSR compare 0x14 */
fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
fwohcireg_t bus_id; /* BUS_ID 0x1c */
fwohcireg_t bus_opt; /* BUS option 0x20 */
fwohcireg_t guid_hi; /* GUID hi 0x24 */
fwohcireg_t guid_lo; /* GUID lo 0x28 */
fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
fwohcireg_t config_rom; /* config ROM map 0x34 */
fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
fwohcireg_t vender; /* vender ID 0x40 */
fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
fwohcireg_t dummy3[1]; /* dummy 0x60 */
fwohcireg_t sid_buf; /* self id buffer 0x64 */
fwohcireg_t sid_cnt; /* self id count 0x68 */
fwohcireg_t dummy4[1]; /* dummy 0x6c */
fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
fwohcireg_t int_stat; /* 0x80 */
fwohcireg_t int_clear; /* 0x84 */
fwohcireg_t int_mask; /* 0x88 */
fwohcireg_t int_mask_clear; /* 0x8c */
fwohcireg_t it_int_stat; /* 0x90 */
fwohcireg_t it_int_clear; /* 0x94 */
fwohcireg_t it_int_mask; /* 0x98 */
fwohcireg_t it_mask_clear; /* 0x9c */
fwohcireg_t ir_int_stat; /* 0xa0 */
fwohcireg_t ir_int_clear; /* 0xa4 */
fwohcireg_t ir_int_mask; /* 0xa8 */
fwohcireg_t ir_mask_clear; /* 0xac */
fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
fwohcireg_t fairness; /* fairness control 0xdc */
fwohcireg_t link_cntl; /* Chip control 0xe0*/
fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
fwohcireg_t node; /* Node ID 0xe8 */
fwohcireg_t phy_access; /* PHY cntl 0xec */
fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */