emuxki_reg_read_32
LOG(("EMU_IPR = %#08x\n",emuxki_reg_read_32(config, EMU_IPR)));
LOG(("EMU_INTE = %#08x\n",emuxki_reg_read_32(config, EMU_INTE)));
LOG(("EMU_HCFG = %#08x\n",emuxki_reg_read_32(config, EMU_HCFG)));
(emuxki_reg_read_32(&card->config, EMU_A_IOCFG)
(emuxki_reg_read_32(&card->config, EMU_A_IOCFG)
(emuxki_reg_read_32(&card->config, EMU_HCFG) & ~EMU_HCFG_GPOUTPUT0));
while ((ipr = emuxki_reg_read_32(&card->config, EMU_IPR))) {
while ((ipr = emuxki_reg_read_32(&card->config, EMU_A2_IPR2))) {
while ((ipr = emuxki_reg_read_32(&card->config, EMU_A2_IPR3))) {
EMU_A_IOCFG_GPOUT0 | emuxki_reg_read_32(&card->config, EMU_A_IOCFG));
emuxki_reg_read_32(&card->config, EMU_A_IOCFG) & ~0x8);
emuxki_reg_read_32(config, EMU_INTE) | value);
emuxki_reg_read_32(config, EMU_INTE) & ~value);
return emuxki_reg_read_32(config, EMU_A2_DATA);
uint32 emuxki_reg_read_32(device_config *config, int regno);
emuxki_reg_read_32(&(port->card->config), EMU_INTE) | EMU_INTE_MIDIRXENABLE );
emuxki_reg_read_32(&port->card->config, EMU_INTE) & ~ EMU_INTE_MIDIRXENABLE);
LOG(("EMU_IPR = %#08x\n",emuxki_reg_read_32(&card->config, EMU_IPR)));
LOG(("EMU_INTE = %#08x\n",emuxki_reg_read_32(&card->config, EMU_INTE)));
LOG(("EMU_HCFG = %#08x\n",emuxki_reg_read_32(&card->config, EMU_HCFG)));