headers/os/add-ons/graphics/Accelerant.h

113

display_timing timing; /* CTRC info */

headers/private/graphics/common/compute_display_timing.h

18

bool interlaced, display_timing* timing);

headers/private/graphics/intel_extreme/intel_extreme.h

429

display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS

headers/private/graphics/nvidia/DriverInterface.h

258

display_timing timing; /* 'native modeline' fetched for screen */

headers/private/graphics/nvidia/DriverInterface.h

373

display_timing p1_timing; /* 'modeline' fetched for panel at CRTC1 */

headers/private/graphics/nvidia/DriverInterface.h

374

display_timing p2_timing; /* 'modeline' fetched for panel at CRTC2 */

headers/private/graphics/skeleton/DriverInterface.h

245

display_timing p1_timing; /* 'modeline' fetched for panel 1 */

headers/private/graphics/skeleton/DriverInterface.h

246

display_timing p2_timing; /* 'modeline' fetched for panel 2 */

headers/private/graphics/via/DriverInterface.h

256

display_timing p1_timing; /* 'modeline' fetched for panel 1 */

headers/private/graphics/via/DriverInterface.h

257

display_timing p2_timing; /* 'modeline' fetched for panel 2 */

src/add-ons/accelerants/common/compute_display_timing.cpp

141

bool interlaced, display_timing* timing)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

247

FDILink::PreTrain(display_timing* target, uint32* linkBandwidth, uint32* lanes, uint32* bitsPerPixel)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp

327

FDILink::Train(display_timing* target, uint32 lanes)

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h

69

display_timing* target,

src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h

73

status_t Train(display_timing* target, uint32 lanes);

src/add-ons/accelerants/intel_extreme/PanelFitter.cpp

81

PanelFitter::Enable(const display_timing& timing)

src/add-ons/accelerants/intel_extreme/PanelFitter.h

20

void Enable(const display_timing& timing);

src/add-ons/accelerants/intel_extreme/Pipes.cpp

234

Pipe::SetFDILink(const display_timing& timing, uint32 linkBandwidth, uint32 lanes, uint32 bitsPerPixel)

src/add-ons/accelerants/intel_extreme/Pipes.h

44

const display_timing& timing,

src/add-ons/accelerants/intel_extreme/Ports.cpp

1239

display_timing hardwareTarget;

src/add-ons/accelerants/intel_extreme/Ports.cpp

1842

DisplayPort::_SetPortLinkGen4(const display_timing& timing)

src/add-ons/accelerants/intel_extreme/Ports.cpp

1905

DisplayPort::_SetPortLinkGen6(const display_timing& timing)

src/add-ons/accelerants/intel_extreme/Ports.cpp

2030

display_timing hardwareTarget = target->timing;

src/add-ons/accelerants/intel_extreme/Ports.cpp

2469

DigitalDisplayInterface::_SetPortLinkGen8(const display_timing& timing, uint32 pllSel)

src/add-ons/accelerants/intel_extreme/Ports.cpp

2617

display_timing hardwareTarget = target->timing;

src/add-ons/accelerants/intel_extreme/Ports.h

208

status_t _SetPortLinkGen4(const display_timing& timing);

src/add-ons/accelerants/intel_extreme/Ports.h

209

status_t _SetPortLinkGen6(const display_timing& timing);

src/add-ons/accelerants/intel_extreme/Ports.h

250

status_t _SetPortLinkGen8(const display_timing& timing,

src/add-ons/accelerants/intel_extreme/pll.cpp

187

lvds_dual_link(display_timing* current)

src/add-ons/accelerants/intel_extreme/pll.cpp

218

compute_pll_p2(display_timing* current, pll_divisors* divisors,

src/add-ons/accelerants/intel_extreme/pll.cpp

272

compute_dpll_g4x(display_timing* current, pll_divisors* divisors, bool isLVDS)

src/add-ons/accelerants/intel_extreme/pll.cpp

366

compute_dpll_9xx(display_timing* current, pll_divisors* divisors, bool isLVDS)

src/add-ons/accelerants/intel_extreme/pll.cpp

450

compute_pll_divisors(display_timing* current, pll_divisors* divisors, bool isLVDS)

src/add-ons/accelerants/intel_extreme/pll.h

45

void compute_pll_divisors(display_timing* current, pll_divisors* divisors,

src/add-ons/accelerants/radeon/impactv.c

285

display_timing *timing, tv_standard_e tv_format )

src/add-ons/accelerants/radeon/monitor_detection.c

785

const display_timing *timing = &vesa_mode_list[best_fit];

src/add-ons/accelerants/radeon/radeon_accelerant.h

75

extern const display_timing vesa_mode_list[];

src/add-ons/accelerants/radeon/vesa_modes.c

7

const display_timing vesa_mode_list[] = {

src/add-ons/accelerants/radeon_hd/connector.cpp

234

display_timing* timing = &mode->timing;

src/add-ons/accelerants/radeon_hd/display.cpp

905

display_timing& displayTiming = mode->timing;

src/add-ons/accelerants/radeon_hd/display.cpp

948

display_timing& displayTiming = mode->timing;

src/add-ons/kernel/drivers/graphics/intel_extreme/bios.cpp

455

sanitize_panel_timing(display_timing& timing)

src/add-ons/kernel/drivers/graphics/intel_extreme/bios.cpp

486

display_timing* panelTiming = &info->panel_timing;

src/bin/screenmode/screenmode.cpp

68

const display_timing& timing = displayMode.timing;

src/servers/app/Screen.cpp

110

const display_timing& timing)

src/servers/app/Screen.h

38

const display_timing& timing);