dpcd_reg_read
dpcd_reg_read(id, DP_MAX_LANE_COUNT) & DP_MAX_LANE_COUNT_MASK);
dpcd_reg_read(id, DP_MAX_LINK_RATE));
dpcd_reg_read(id, DP_NORP) & DP_NORP_MASK);
dpcd_reg_read(id, DP_DOWNSTREAMPORT_PRESENT) & DP_DWN_STRM_PORT_PRESENT
dpcd_reg_read(id, DP_DOWN_STREAM_PORT_COUNT)
= dp_decode_link_rate(dpcd_reg_read(connectorIndex, DP_MAX_LINK_RATE));
uint32 dpMaxLaneCount = dpcd_reg_read(connectorIndex,
return dp_decode_link_rate(dpcd_reg_read(connectorIndex, DP_MAX_LINK_RATE));
dp->revision = dpcd_reg_read(connectorIndex, DP_DPCD_REV);
= dpcd_reg_read(connectorIndex, DP_TRAINING_AUX_RD_INTERVAL);
uint8 sandbox = dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT);
if ((dpcd_reg_read(connectorIndex, DP_MAX_DOWNSPREAD) & 0x1) != 0) {
sandbox = dpcd_reg_read(connectorIndex, DP_LANE_COUNT);
&& (dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT)
uint8 dpcd_reg_read(uint32 connectorIndex, uint32 address);
id[bit] = dpcd_reg_read(dp->auxPin, 0x503 + bit);