bus_write_2
bus_write_2((_sc)->alc_res[0], (reg), (val))
bus_write_2((_sc)->ale_res[0], (reg), (val))
bus_write_2((_sc)->age_res[0], (reg), (val))
bus_write_2((sc)->mem[0], (reg), (val))
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
bus_write_2((sc)->msk_res[0], (reg), (val))
bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_write_2(lesc->sc_rres, PCNET_PCI_BDP, val);
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_write_2(lesc->sc_rres, PCNET_PCI_RDP, val);
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, LE_CSR0);
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, LE_CSR0);
bus_write_2(lesc->sc_rres, PCNET_PCI_RDP, isr & ~(LE_C0_INEA));
bus_write_2((_sc)->vte_res, (reg), (val))
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
bus_write_2((sc)->sk_res[0], (reg), (val))
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val)
bus_write_2(sc->vge_res, reg, val)
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->port_res, reg, val)
#define CSR_MEM_WRITE_2(sc, reg, val) bus_write_2(sc->mem_res, reg, val)